-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_ram is
        generic (
            ADDR_WIDTH      : natural := 8;
            DATA_WIDTH      : natural := 12;
            MEMORY_DEPTH    : natural := 256
        );
        port (
            clk         : in std_logic;
            addr        : in std_logic_vector(ADDR_WIDTH-1 downto 0);
            wen         : in std_logic;
            ren         : in std_logic;
            wr_data     : in std_logic_vector(DATA_WIDTH-1 downto 0);
            rd_data     : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end entity;

architecture arch of single_port_ram is
    
    type RAM_TYPE is array (0 to MEMORY_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
    
    signal mem : RAM_TYPE := (others => (others => '0'));
    
begin
    
    ram_prc : process(all)
    begin
        if rising_edge(clk) then
            rd_data <= (others => '0');
            
            -- Read-During-Write not supported
            assert(wen = '1' nand ren = '1') severity FAILURE;
            
            if (wen = '1') then
                mem(to_integer(unsigned(addr))) <= wr_data;
            end if;
            
            if (ren = '1') then
                rd_data <= mem(to_integer(unsigned(addr)));
            end if;
        end if;
    end process;

end architecture;