onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l0_rtps_writer_test2/uut/clk
add wave -noupdate /l0_rtps_writer_test2/uut/reset
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/time
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/check_time
add wave -noupdate -divider INPUT
add wave -noupdate -expand -group META /l0_rtps_writer_test2/uut/empty_meta
add wave -noupdate -expand -group META /l0_rtps_writer_test2/uut/rd_meta
add wave -noupdate -expand -group META /l0_rtps_writer_test2/uut/last_word_in_meta
add wave -noupdate -expand -group META -radix hexadecimal /l0_rtps_writer_test2/uut/data_in_meta
add wave -noupdate -group USER /l0_rtps_writer_test2/uut/empty_user
add wave -noupdate -group USER /l0_rtps_writer_test2/uut/rd_user
add wave -noupdate -group USER -radix hexadecimal /l0_rtps_writer_test2/uut/data_in_user
add wave -noupdate -group USER /l0_rtps_writer_test2/uut/last_word_in_user
add wave -noupdate -divider {MAIN FSM}
add wave -noupdate /l0_rtps_writer_test2/uut/stage
add wave -noupdate /l0_rtps_writer_test2/uut/cnt
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/ind
add wave -noupdate /l0_rtps_writer_test2/uut/w_map
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/last_seq_nr
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/global_ack_seq_nr_base
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/next_seq_nr
add wave -noupdate -divider {MEMORY FSM}
add wave -noupdate /l0_rtps_writer_test2/uut/mem_op_done
add wave -noupdate /l0_rtps_writer_test2/uut/mem_op_start
add wave -noupdate /l0_rtps_writer_test2/uut/mem_opcode
add wave -noupdate /l0_rtps_writer_test2/uut/mem_stage
add wave -noupdate /l0_rtps_writer_test2/uut/mem_cnt
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/mem_occupied_head
add wave -noupdate -radix unsigned /l0_rtps_writer_test2/uut/mem_empty_head
add wave -noupdate -radix unsigned -childformat {{/l0_rtps_writer_test2/uut/mem_addr_base(5) -radix unsigned} {/l0_rtps_writer_test2/uut/mem_addr_base(4) -radix unsigned} {/l0_rtps_writer_test2/uut/mem_addr_base(3) -radix unsigned} {/l0_rtps_writer_test2/uut/mem_addr_base(2) -radix unsigned} {/l0_rtps_writer_test2/uut/mem_addr_base(1) -radix unsigned} {/l0_rtps_writer_test2/uut/mem_addr_base(0) -radix unsigned}} -subitemconfig {/l0_rtps_writer_test2/uut/mem_addr_base(5) {-height 15 -radix unsigned} /l0_rtps_writer_test2/uut/mem_addr_base(4) {-height 15 -radix unsigned} /l0_rtps_writer_test2/uut/mem_addr_base(3) {-height 15 -radix unsigned} /l0_rtps_writer_test2/uut/mem_addr_base(2) {-height 15 -radix unsigned} /l0_rtps_writer_test2/uut/mem_addr_base(1) {-height 15 -radix unsigned} /l0_rtps_writer_test2/uut/mem_addr_base(0) {-height 15 -radix unsigned}} /l0_rtps_writer_test2/uut/mem_addr_base
add wave -noupdate -childformat {{/l0_rtps_writer_test2/uut/mem_endpoint_data.addr -radix hexadecimal} {/l0_rtps_writer_test2/uut/mem_endpoint_data.guid -radix hexadecimal} {/l0_rtps_writer_test2/uut/mem_endpoint_data.portn -radix hexadecimal} {/l0_rtps_writer_test2/uut/mem_endpoint_data.lease_deadline -radix hexadecimal} {/l0_rtps_writer_test2/uut/mem_endpoint_data.res_time -radix unsigned} {/l0_rtps_writer_test2/uut/mem_endpoint_data.ack_seq_nr_base -radix unsigned} {/l0_rtps_writer_test2/uut/mem_endpoint_data.req_seq_nr_base -radix unsigned}} -subitemconfig {/l0_rtps_writer_test2/uut/mem_endpoint_data.addr {-height 15 -radix hexadecimal} /l0_rtps_writer_test2/uut/mem_endpoint_data.guid {-height 15 -radix hexadecimal} /l0_rtps_writer_test2/uut/mem_endpoint_data.portn {-height 15 -radix hexadecimal} /l0_rtps_writer_test2/uut/mem_endpoint_data.lease_deadline {-height 15 -radix hexadecimal} /l0_rtps_writer_test2/uut/mem_endpoint_data.res_time {-height 15 -radix unsigned} /l0_rtps_writer_test2/uut/mem_endpoint_data.ack_seq_nr_base {-height 15 -radix unsigned} /l0_rtps_writer_test2/uut/mem_endpoint_data.req_seq_nr_base {-height 15 -radix unsigned}} /l0_rtps_writer_test2/uut/mem_endpoint_data
add wave -noupdate -expand -group MEM0 -radix unsigned /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/addr
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/read
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/ready_in
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/valid_in
add wave -noupdate -expand -group MEM0 -radix hexadecimal /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/data_in
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/ready_out
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/valid_out
add wave -noupdate -expand -group MEM0 -radix hexadecimal /l0_rtps_writer_test2/uut/mem_ctrl_gen(0)/mem_ctrl_inst/data_out
add wave -noupdate -group MEM1 -radix unsigned /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/addr
add wave -noupdate -group MEM1 /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/read
add wave -noupdate -group MEM1 /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/ready_in
add wave -noupdate -group MEM1 /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/valid_in
add wave -noupdate -group MEM1 -radix hexadecimal /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/data_in
add wave -noupdate -group MEM1 /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/ready_out
add wave -noupdate -group MEM1 /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/valid_out
add wave -noupdate -group MEM1 -radix hexadecimal /l0_rtps_writer_test2/uut/mem_ctrl_gen(1)/mem_ctrl_inst/data_out
add wave -noupdate -divider TESTBENCH
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/start_meta
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/packet_sent_meta
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/start_user
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/packet_sent_user
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/check_trigger
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/mem_check_done
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/stim_done
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test2/test_done
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {Cursor {7514599 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 135
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {7163585 ps} {8165489 ps}