library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library osvvm; -- Utility Library context osvvm.OsvvmContext; use work.rtps_package.all; use work.user_config.all; use work.rtps_config_package.all; use work.rtps_test_package.all; -- This testbench tests the metatraffic operation behaviour of the RTPS Reader. (Remote Endpoint matching and memory behaviour) -- This testbench is using external names to access the memory of the rtps_reader directly and check the contents at the supposed locations. -- This testbench covers following: -- * Mathing Endpoint -- * Memory Full Behaviour -- * Unmatching Endpoint -- * Unmatching Participant -- * Updating previously matched Endpoint -- * Unknown Metatraffic Operation entity L0_rtps_reader_test1 is end entity; architecture testbench of L0_rtps_reader_test1 is -- *CONSTANT DECLARATION* constant MAX_REMOTE_ENDPOINTS : natural := 3; -- *TYPE DECLARATION* type TEST_STAGE_TYPE is (IDLE, BUSY); type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*WRITER_ENDPOINT_FRAME_SIZE_A)-1) of std_logic_vector(WORD_WIDTH-1 downto 0); -- *SIGNAL DECLARATION* signal clk, empty_user, empty_meta, rd_meta, last_word_in_meta : std_logic := '0'; signal reset : std_logic := '1'; signal data_in_meta, data_out_hc : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0'); signal start_hc, ack_hc, done_hc, done_hc_delay : std_logic := '0'; signal opcode_hc : HISTORY_CACHE_OPCODE_TYPE := NOP; signal ret_hc : HISTORY_CACHE_RESPONSE_TYPE := OK; signal stim_stage : TEST_STAGE_TYPE := IDLE; shared variable stimulus, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET; signal packet_sent : std_logic := '0'; signal cnt_stim : natural := 0; signal start : std_logic := '0'; shared variable SB_out : osvvm.ScoreBoardPkg_slv.ScoreBoardPType; shared variable SB_mem : work.ScoreBoardPkg_MemoryTest.ScoreBoardPType; signal stim_done, mem_check_done, out_check_done, test_done : std_logic := '0'; -- *FUNCTION DECLARATION* procedure wait_on_sent is begin wait until rising_edge(packet_sent); end procedure; procedure wait_on_mem_check is begin if (mem_check_done /= '1') then wait until mem_check_done = '1'; end if; end procedure; procedure wait_on_completion is begin if (test_done /= '1') then wait until test_done = '1'; end if; end procedure; begin -- Unit Under Test uut : entity work.rtps_reader(arch) generic map ( ENTITYID => DEFAULT_READER_ENTITYID, RELIABILTY_QOS => RELIABLE_RELIABILITY_QOS, LIVELINESS_QOS => AUTOMATIC_LIVELINESS_QOS, DURABILITY_QOS => VOLATILE_DURABILITY_QOS, HEARTBEAT_RESPONSE_DELAY => DURATION_ZERO, HEARTBEAT_SUPPRESSION_DELAY => DURATION_ZERO, LEASE_DURATION => DURATION_INFINITE, WITH_KEY => TRUE, MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS ) port map ( -- SYSTEM clk => clk, reset => reset, time => TIME_ZERO, empty_user => '1', rd_user => open, data_in_user => (others => '0'), last_word_in_user => '0', empty_meta => empty_meta or packet_sent, rd_meta => rd_meta, data_in_meta => data_in_meta, last_word_in_meta => last_word_in_meta, wr_rtps => open, full_rtps => '0', last_word_out_rtps => open, data_out_rtps => open, start_hc => start_hc, opcode_hc => opcode_hc, ack_hc => ack_hc, done_hc => done_hc, ret_hc => ret_hc, data_out_hc => data_out_hc, valid_out_hc => open, ready_out_hc => '0', last_word_out_hc => open ); stimulus_prc : process variable RV : RandomPType; variable p0, p1, participant : PARTICIPANT_DATA_TYPE := DEFAULT_PARTICIPANT_DATA; variable e0, e1, e2, e3, endpoint : ENDPOINT_DATA_TYPE := DEFAULT_ENDPOINT_DATA; -- Wrapper to use procedure as function impure function gen_rand_loc_2 return LOCATOR_TYPE is variable ret : LOCATOR_TYPE := EMPTY_LOCATOR; begin gen_rand_loc(RV, ret); return ret; end function; impure function gen_rand_guid_prefix return GUIDPREFIX_TYPE is variable ret : GUIDPREFIX_TYPE; begin ret := (0 => RV.RandSlv(WORD_WIDTH), 1 => RV.RandSlv(WORD_WIDTH), 2 => RV.RandSlv(WORD_WIDTH)); return ret; end function; procedure start_test is begin start <= '1'; wait until rising_edge(clk); start <= '0'; wait until rising_edge(clk); end procedure; begin SetAlertLogName("rtps_reader - Level 0 - Metatraffic Handling"); SetAlertEnable(FAILURE, TRUE); SetAlertEnable(ERROR, TRUE); SetAlertEnable(WARNING, TRUE); SetLogEnable(DEBUG, FALSE); SetLogEnable(PASSED, FALSE); SetLogEnable(INFO, TRUE); RV.InitSeed(RV'instance_name); p0.guidPrefix := gen_rand_guid_prefix; p1.guidPrefix := gen_rand_guid_prefix; -- Endpoint 1 e0 := DEFAULT_ENDPOINT_DATA; e0.participant := p0; e0.entityid := RV.RandSlv(ENTITYID_WIDTH); e0.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR)); -- Endpoint 2 e1 := DEFAULT_ENDPOINT_DATA; e1.participant := p0; e1.entityid := RV.RandSlv(ENTITYID_WIDTH); e1.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR)); -- Endpoint 3 e2 := DEFAULT_ENDPOINT_DATA; e2.participant := p1; e2.entityid := RV.RandSlv(ENTITYID_WIDTH); e2.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR)); -- Endpoint 4 e3 := DEFAULT_ENDPOINT_DATA; e3.participant := p1; e3.entityid := RV.RandSlv(ENTITYID_WIDTH); e3.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR)); Log("Initiating Test", INFO); stim_done <= '0'; start <= '0'; reset <= '1'; wait until rising_edge(clk); wait until rising_edge(clk); reset <= '0'; Log("Insert Endpoint 0 Participant 0", INFO); endpoint := e0; endpoint.nr := 0; endpoint.match := MATCH; gen_endpoint_match_frame(endpoint, stimulus); SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p0e0,0,0] Log("Insert Endpoint 1 Participant 0", INFO); endpoint := e1; endpoint.nr := 1; endpoint.match := MATCH; gen_endpoint_match_frame(endpoint, stimulus); SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p0e0,p0e1,0] Log("Insert Endpoint 2 Participant 1", INFO); endpoint := e2; endpoint.nr := 2; endpoint.match := MATCH; gen_endpoint_match_frame(endpoint, stimulus); SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p0e0,p0e1,p1e2] Log("Ignore Endpoint 3 Participant 1 [Memory Full]", INFO); endpoint := e3; endpoint.match := MATCH; gen_endpoint_match_frame(endpoint, stimulus); -- Re-check Mem-State endpoint := e0; endpoint.nr := 0; endpoint.match := MATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); endpoint := e1; endpoint.nr := 1; endpoint.match := MATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); endpoint := e2; endpoint.nr := 2; endpoint.match := MATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p0e0,p0e1,p1e3] Log("Remove Endpoint 2 Participant 1", INFO); endpoint := e2; endpoint.nr := 2; endpoint.match := UNMATCH; gen_endpoint_match_frame(endpoint, stimulus); SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); SB_out.Push(std_logic_vector(to_unsigned(endpoint.nr, WORD_WIDTH))); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p0e0,p0e1,0] Log("Insert Endpoint 3 Participant 1", INFO); endpoint := e3; endpoint.nr := 2; endpoint.match := MATCH; gen_endpoint_match_frame(endpoint, stimulus); SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p0e0,p0e1,p1e3] Log("Remove Participant 0", INFO); participant := p0; participant.match := UNMATCH; gen_participant_match_frame(participant, stimulus); -- Remove Endpoint 0 endpoint := e0; endpoint.nr := 0; endpoint.match := UNMATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); SB_out.Push(std_logic_vector(to_unsigned(endpoint.nr, WORD_WIDTH))); -- Remove Endpoint 1 endpoint := e1; endpoint.nr := 1; endpoint.match := UNMATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); SB_out.Push(std_logic_vector(to_unsigned(endpoint.nr, WORD_WIDTH))); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [0,0,p1e3] Log("Insert Endpoint 2 Participant 1", INFO); endpoint := e2; endpoint.nr := 0; endpoint.match := MATCH; gen_endpoint_match_frame(endpoint, stimulus); SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p1e2,0,p1e3] Log("Unknown Metatraffic Operation followed by insertion of Enpoint 0 Participant 0", INFO); for i in 0 to 9 loop stimulus.data(i) := RV.RandSlv(WORD_WIDTH); end loop; stimulus.last(9) := '1'; stimulus.length := 10; endpoint := e0; endpoint.nr := 1; endpoint.match := MATCH; gen_endpoint_match_frame(endpoint, stimulus); -- Re-check Mem-State endpoint := e2; endpoint.nr := 0; endpoint.match := MATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); endpoint := e0; endpoint.nr := 1; endpoint.match := MATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); endpoint := e3; endpoint.nr := 2; endpoint.match := MATCH; SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p1e2,p0e0,p1e3] Log("Update Endpoint 2 Participant 1", INFO); endpoint := e2; endpoint.nr := 0; endpoint.match := MATCH; endpoint.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR)); gen_endpoint_match_frame(endpoint, stimulus); SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint)); start_test; wait_on_sent; stimulus := EMPTY_TEST_PACKET; wait_on_mem_check; -- MEMORY STATE [p1e2,p0e0,p1e3] stim_done <= '1'; wait_on_completion; TranscriptOpen(RESULTS_FILE, APPEND_MODE); SetTranscriptMirror; ReportAlerts; TranscriptClose; std.env.stop; wait; end process; clock_prc : process begin clk <= '0'; wait for 25 ns; clk <= '1'; wait for 25 ns; end process; in_empty_prc : process begin empty_meta <= '0'; wait until rd_meta = '1'; wait until rising_edge(clk); empty_meta <= '1'; wait until rising_edge(clk); end process; alert_prc : process(all) begin if rising_edge(clk) then alertif(empty_meta = '1' and rd_meta = '1', "Input FIFO read signal high while empty signal high", ERROR); end if; end process; input_prc : process(all) begin data_in_meta <= stimulus.data(cnt_stim); last_word_in_meta <= stimulus.last(cnt_stim); if rising_edge(clk) then if (reset = '1') then cnt_stim <= 0; stim_stage <= IDLE; packet_sent <= '1'; else case (stim_stage) is when IDLE => if (start = '1' and stimulus.length /= 0) then stim_stage <= BUSY; packet_sent <= '0'; end if; when BUSY => if (rd_meta = '1') then if (cnt_stim = stimulus.length-1) then stim_stage <= IDLE; packet_sent <= '1'; cnt_stim <= 0; else cnt_stim <= cnt_stim + 1; end if; end if; end case; end if; end if; end process; done_proc : process(clk) begin if rising_edge(clk) then if (stim_done = '1' and SB_out.empty and SB_mem.empty) then test_done <= '1'; else test_done <= '0'; end if; end if; end process; out_check_prc : process(all) begin if rising_edge(clk) then done_hc <= done_hc_delay; if (start_hc = '1') then ack_hc <= '1'; done_hc_delay <= '1'; case (opcode_hc) is when REMOVE_WRITER => SB_out.check(data_out_hc); when others => Alert("Unexpected HC Opcode", ERROR); end case; else ack_hc <= '0'; done_hc_delay <= '0'; end if; end if; end process; mem_check_prc : process alias mem is <>; alias mem_op_done is <>; alias idle_sig is <>; variable reference : TEST_WRITER_ENDPOINT_MEMORY_FRAME_TYPE_A; begin mem_check_done <= '0'; -- SAFEGUARD: (Prevent Fall-through Behavior) if (reset /= '0') then wait until reset = '0'; end if; -- Wait for Packet to be sent wait until rising_edge(packet_sent); -- Wait for UUT IDLE state if (idle_sig /= '1') then wait until idle_sig = '1'; end if; -- Wait for ongoing memory operation if (mem_op_done /= '1') then wait until mem_op_done = '1'; end if; while (not SB_mem.empty) loop SB_mem.Pop(reference); for i in 0 to reference'length-1 loop AffirmIf(?? (mem(reference(i).addr) ?= reference(i).data), "Address: " & integer'image(reference(i).addr) & " Received: " & to_hstring(mem(reference(i).addr)) & " Expected: " & to_hstring(reference(i).data)); end loop; end loop; -- Toggle High for one clock cycle mem_check_done <= '1'; wait until rising_edge(clk); end process; watchdog : process begin wait for 1 ms; Alert("Test timeout", FAILURE); std.env.stop; end process; end architecture;