library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Library xpm;
use xpm.vcomponents.all;

entity single_port_ram is
        generic (
            ADDR_WIDTH      : integer := 8;
            DATA_WIDTH      : integer := 12;
            MEMORY_SIZE     : integer := DATA_WIDTH*(2**ADDR_WIDTH)
            
        );
        port (
            clk         : in std_logic;
            addr        : in std_logic_vector(ADDR_WIDTH-1 downto 0);
            wen         : in std_logic;
            ren         : in std_logic;
            wr_data     : in std_logic_vector(DATA_WIDTH-1 downto 0);
            rd_data     : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end entity;

architecture arch of single_port_ram is
    
begin

    xpm_memory_spram_inst : xpm_memory_spram
        generic map (
            ADDR_WIDTH_A        => ADDR_WIDTH,
            AUTO_SLEEP_TIME     => 0,
            BYTE_WRITE_WIDTH_A  => DATA_WIDTH,
            ECC_MODE            => "no_ecc",
            MEMORY_INIT_FILE    => "none",
            MEMORY_INIT_PARAM   => "0",
            MEMORY_OPTIMIZATION => "true",
            MEMORY_PRIMITIVE    => "auto",
            MEMORY_SIZE         => MEMORY_SIZE,
            MESSAGE_CONTROL     => 0,
            READ_DATA_WIDTH_A   => DATA_WIDTH,
            READ_LATENCY_A      => 1,
            READ_RESET_VALUE_A  => "0",
            RST_MODE_A          => "SYNC",
            USE_MEM_INIT        => 1,
            WAKEUP_TIME         => "disable_sleep",
            WRITE_DATA_WIDTH_A  => DATA_WIDTH,
            WRITE_MODE_A        => "read_first"
        )
        port map (
            dbiterra        => open,
            douta           => rd_data,
            sbiterra        => open,
            addra           => addr,
            clka            => clk,
            dina            => wr_data,
            ena             => (ren or wen),
            injectdbiterra  => '0',
            injectsbiterra  => '0',
            regcea          => '1',
            rsta            => '0',
            sleep           => '0',
            wea             => (others => wen) --1-bit Vector
        );

end architecture;