onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/clk
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/reset
add wave -noupdate -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/time
add wave -noupdate -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/check_time
add wave -noupdate -divider INPUT
add wave -noupdate -group META /l1_rtps_writer_test2_vrkdn/uut/empty_meta
add wave -noupdate -group META /l1_rtps_writer_test2_vrkdn/uut/rd_meta
add wave -noupdate -group META /l1_rtps_writer_test2_vrkdn/uut/last_word_in_meta
add wave -noupdate -group META -radix hexadecimal /l1_rtps_writer_test2_vrkdn/uut/data_in_meta
add wave -noupdate -group USER /l1_rtps_writer_test2_vrkdn/uut/empty_user
add wave -noupdate -group USER /l1_rtps_writer_test2_vrkdn/uut/rd_user
add wave -noupdate -group USER -radix hexadecimal /l1_rtps_writer_test2_vrkdn/uut/data_in_user
add wave -noupdate -group USER /l1_rtps_writer_test2_vrkdn/uut/last_word_in_user
add wave -noupdate -divider HC
add wave -noupdate -expand -group HC /l1_rtps_writer_test2_vrkdn/uut/data_available
add wave -noupdate -expand -group HC /l1_rtps_writer_test2_vrkdn/uut/start_hc
add wave -noupdate -expand -group HC /l1_rtps_writer_test2_vrkdn/uut/opcode_hc
add wave -noupdate -expand -group HC /l1_rtps_writer_test2_vrkdn/uut/ack_hc
add wave -noupdate -expand -group HC -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/seq_nr_hc
add wave -noupdate -expand -group HC /l1_rtps_writer_test2_vrkdn/uut/done_hc
add wave -noupdate -expand -group HC /l1_rtps_writer_test2_vrkdn/uut/ret_hc
add wave -noupdate -expand -group HC -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/cc_seq_nr
add wave -noupdate -divider OUTPUT
add wave -noupdate -group {RTPS OUT} /l1_rtps_writer_test2_vrkdn/uut/full_ro
add wave -noupdate -group {RTPS OUT} /l1_rtps_writer_test2_vrkdn/uut/wr_ro
add wave -noupdate -group {RTPS OUT} -radix hexadecimal /l1_rtps_writer_test2_vrkdn/uut/data_out_ro
add wave -noupdate -group {RTPS OUT} /l1_rtps_writer_test2_vrkdn/uut/last_word_out_ro
add wave -noupdate /l1_rtps_writer_test2_vrkdn/rtps_out_inst/wr
add wave -noupdate -radix hexadecimal /l1_rtps_writer_test2_vrkdn/rtps_out_inst/data_out
add wave -noupdate -divider {MAIN FSM}
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/stage
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/stage_next
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/cnt
add wave -noupdate -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/last_seq_nr
add wave -noupdate -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/global_ack_seq_nr_base
add wave -noupdate -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/next_seq_nr
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/assert_liveliness_latch
add wave -noupdate -divider {MEMORY FSM}
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/mem_op_done
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/mem_op_start
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/mem_opcode
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/mem_stage
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/mem_stage_next
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/mem_cnt
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/mem_pos
add wave -noupdate -radix unsigned -childformat {{/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(6) -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(5) -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(4) -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(3) -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(2) -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(1) -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(0) -radix unsigned}} -subitemconfig {/l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(6) {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(5) {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(4) {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(3) {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(2) {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(1) {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_addr_base(0) {-height 15 -radix unsigned}} /l1_rtps_writer_test2_vrkdn/uut/mem_addr_base
add wave -noupdate -childformat {{/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.guid -radix hexadecimal} {/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.addr -radix hexadecimal} {/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.portn -radix hexadecimal} {/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.lease_deadline -radix hexadecimal} {/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.res_time -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.ack_seq_nr_base -radix unsigned} {/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.req_seq_nr_base -radix unsigned}} -subitemconfig {/l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.guid {-height 15 -radix hexadecimal} /l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.addr {-height 15 -radix hexadecimal} /l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.portn {-height 15 -radix hexadecimal} /l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.lease_deadline {-height 15 -radix hexadecimal} /l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.res_time {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.ack_seq_nr_base {-height 15 -radix unsigned} /l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data.req_seq_nr_base {-height 15 -radix unsigned}} /l1_rtps_writer_test2_vrkdn/uut/mem_endpoint_data
add wave -noupdate -group MEM_CTRL -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/mem_addr
add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test2_vrkdn/uut/mem_valid_in
add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test2_vrkdn/uut/mem_ready_in
add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test2_vrkdn/uut/mem_read
add wave -noupdate -group MEM_CTRL -radix hexadecimal /l1_rtps_writer_test2_vrkdn/uut/mem_write_data
add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test2_vrkdn/uut/abort_read
add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test2_vrkdn/uut/mem_valid_out
add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test2_vrkdn/uut/mem_ready_out
add wave -noupdate -group MEM_CTRL -radix hexadecimal /l1_rtps_writer_test2_vrkdn/uut/mem_read_data
add wave -noupdate -divider TESTBENCH
add wave -noupdate -group TESTBENCH /l1_rtps_writer_test2_vrkdn/start_meta
add wave -noupdate -group TESTBENCH /l1_rtps_writer_test2_vrkdn/packet_sent_meta
add wave -noupdate -group TESTBENCH /l1_rtps_writer_test2_vrkdn/stage_hc
add wave -noupdate -group TESTBENCH /l1_rtps_writer_test2_vrkdn/out_check_done
add wave -noupdate -group TESTBENCH /l1_rtps_writer_test2_vrkdn/stim_done
add wave -noupdate -group TESTBENCH /l1_rtps_writer_test2_vrkdn/test_done
add wave -noupdate -divider MISC
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/nack_bitmap_pos
add wave -noupdate /l1_rtps_writer_test2_vrkdn/uut/req_seq_nr_bitmap
add wave -noupdate -radix unsigned /l1_rtps_writer_test2_vrkdn/uut/nack_base
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {Begin {49575000 ps} 1} {Error {7325000 ps} 1} {Cursor {12825000 ps} 0}
quietly wave cursor active 3
configure wave -namecolwidth 150
configure wave -valuecolwidth 135
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {12324048 ps} {13325952 ps}