rtps-fpga/syn/test_top.vhd

-- altera vhdl_input_version vhdl_2008
-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.rtps_package.all;
use work.rtps_config_package.all;

entity test_top is
    port (
        -- SYSTEM
        clk         : in std_logic;
        reset       : in std_logic;
        -- AVALON MM INTERFACE
        address     : in std_logic_vector(1 downto 0);
        read        : in std_logic;
        write       : in std_logic;
        readdata    : out std_logic_vector(WORD_WIDTH-1 downto 0);
        writedata   : in std_logic_vector(WORD_WIDTH-1 downto 0);
        waitrequest : out std_logic
    );
end entity;

architecture arch of test_top is
    
    signal full_fi_wr, write_wr_fi, empty_fo_wr, read_wr_fo, empty_fi_test, read_test_fi, full_fo_test, write_test_fo : std_logic;
    signal data_wr_fi, data_fo_wr, data_fi_test, data_test_fo : std_logic_vector(WORD_WIDTH-1 downto 0);
    signal time : TIME_TYPE;
    signal input_util, output_util : natural;
    
begin
    
    Avalon_MM_wrapper_inst : entity work.Avalon_MM_wrapper(arch)
        port map (
            clk         => clk,
            reset       => reset,
            address     => address,
            read        => read,
            write       => write,
            readdata    => readdata,
            writedata   => writedata,
            waitrequest => waitrequest,
            full_ri     => full_fi_wr,
            write_ri    => write_wr_fi,
            data_ri     => data_wr_fi,
            empty_ro    => empty_fo_wr,
            read_ro     => read_wr_fo,
            data_ro     => data_fo_wr
        );
    
    FIFO_IN_inst : configuration work.FWFT_FIFO_cfg
        generic map (
            FIFO_DEPTH  => 16384,
            DATA_WIDTH  => WORD_WIDTH
        )
        port map (
            clk         => clk,
            reset       => reset,
            data_in     => data_wr_fi,
            write       => write_wr_fi,
            read        => read_test_fi,
            data_out    => data_fi_test,
            empty       => empty_fi_test,
            full        => full_fi_wr,
            free        => input_util
        );
    
    FIFO_OUT_inst : configuration work.FWFT_FIFO_cfg
        generic map (
            FIFO_DEPTH  => 16384,
            DATA_WIDTH  => WORD_WIDTH
        )
        port map (
            clk         => clk,
            reset       => reset,
            data_in     => data_test_fo,
            write       => write_test_fo,
            read        => read_wr_fo,
            data_out    => data_fo_wr,
            empty       => empty_fo_wr,
            full        => full_fo_test,
            free        => output_util
        );
    
    --test_fpga_inst : entity work.test_fpga(arch)
    --    port map (
    --        -- SYSTEM
    --        clk         => clk,
    --        reset       => reset,
    --        -- INPUT
    --        empty       => empty_fi_test,
    --        read        => read_test_fi,
    --        data_in     => data_fi_test,
    --        -- OUTPUT
    --        full        => full_fo_test,
    --        write       => write_test_fo,
    --        data_out    => data_test_fo
    --    );
    
    --dds_loopback_inst : entity work.L2_Testbench_Lib4(arch)
    --    port map (
    --        -- SYSTEM
    --        clk         => clk,
    --        reset       => reset,
    --        time        => time,
    --        -- INPUT
    --        empty       => empty_fi_test,
    --        read        => read_test_fi,
    --        data_in     => data_fi_test,
    --        -- OUTPUT
    --        full        => full_fo_test,
    --        write       => write_test_fo,
    --        data_out    => data_test_fo
    --    );
    
    --ros_service_inst : entity work.L2_Testbench_ROS_Lib2(arch)
    --    port map (
    --        -- SYSTEM
    --        clk         => clk,
    --        reset       => reset,
    --        time        => time,
    --        -- INPUT
    --        empty       => empty_fi_test,
    --        read        => read_test_fi,
    --        data_in     => data_fi_test,
    --        -- OUTPUT
    --        full        => full_fo_test,
    --        write       => write_test_fo,
    --        data_out    => data_test_fo
    --    );
    
    --ros_action_inst : entity work.L2_Testbench_ROS_Lib4(arch)
    --    port map (
    --        -- SYSTEM
    --        clk         => clk,
    --        reset       => reset,
    --        time        => time,
    --        -- INPUT
    --        empty       => empty_fi_test,
    --        read        => read_test_fi,
    --        data_in     => data_fi_test,
    --        -- OUTPUT
    --        full        => full_fo_test,
    --        write       => write_test_fo,
    --        data_out    => data_test_fo
    --    );
    
    --ros_rtt_inst : entity work.L2_Testbench_ROS_Lib6(arch)
    --    port map (
    --        -- SYSTEM
    --        clk         => clk,
    --        reset       => reset,
    --        time        => time,
    --        -- UTILIZATION
    --        input_util  => std_logic_vector(to_unsigned(input_util, WORD_WIDTH)),
    --        output_util => std_logic_vector(to_unsigned(output_util, WORD_WIDTH)),
    --        -- INPUT
    --        empty       => empty_fi_test,
    --        read        => read_test_fi,
    --        data_in     => data_fi_test,
    --        -- OUTPUT
    --        full        => full_fo_test,
    --        write       => write_test_fo,
    --        data_out    => data_test_fo
    --    );
    
    loopback_inst : entity work.loopback(arch)
        port map (
            -- SYSTEM
            clk         => clk,
            reset       => reset,
            -- INPUT
            empty       => empty_fi_test,
            rd          => read_test_fi,
            data_in     => data_fi_test,
            -- OUTPUT
            full        => full_fo_test,
            wr          => write_test_fo,
            data_out    => data_test_fo
        );
    
    time_prc : process(clk)
    begin
        if rising_edge(clk) then
            if (reset = '1') then
                time    <= TIME_ZERO;
            else
                time    <= time + CLOCK_DURATION;
            end if;
        end if;
    end process;
    
end architecture;