rtps-fpga/sim/L0_rtps_writer_test2_vrkdp.do
Greek 3ba5fae871 Add Test4 of RTPS Writer
Test remote Reader Liveliness handling of RTPS Writer.
Backport fix to RTPS Reader.
Compiling and Passing
2021-03-03 18:40:36 +01:00

70 lines
6.2 KiB
Plaintext

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/clk
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/reset
add wave -noupdate -radix unsigned /l0_rtps_writer_test2_vrkdp/uut/time
add wave -noupdate -radix unsigned /l0_rtps_writer_test2_vrkdp/uut/check_time
add wave -noupdate -divider INPUT
add wave -noupdate -expand -group META /l0_rtps_writer_test2_vrkdp/uut/empty_meta
add wave -noupdate -expand -group META /l0_rtps_writer_test2_vrkdp/uut/rd_meta
add wave -noupdate -expand -group META /l0_rtps_writer_test2_vrkdp/uut/last_word_in_meta
add wave -noupdate -expand -group META -radix hexadecimal /l0_rtps_writer_test2_vrkdp/uut/data_in_meta
add wave -noupdate -group USER /l0_rtps_writer_test2_vrkdp/uut/empty_user
add wave -noupdate -group USER /l0_rtps_writer_test2_vrkdp/uut/rd_user
add wave -noupdate -group USER -radix hexadecimal /l0_rtps_writer_test2_vrkdp/uut/data_in_user
add wave -noupdate -group USER /l0_rtps_writer_test2_vrkdp/uut/last_word_in_user
add wave -noupdate -divider {MAIN FSM}
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/stage
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/stage_next
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/cnt
add wave -noupdate -radix unsigned /l0_rtps_writer_test2_vrkdp/uut/last_seq_nr
add wave -noupdate -radix unsigned /l0_rtps_writer_test2_vrkdp/uut/global_ack_seq_nr_base
add wave -noupdate -radix unsigned /l0_rtps_writer_test2_vrkdp/uut/next_seq_nr
add wave -noupdate -divider {MEMORY FSM}
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/mem_op_done
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/mem_op_start
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/mem_opcode
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/mem_stage
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/mem_stage_next
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/mem_cnt
add wave -noupdate /l0_rtps_writer_test2_vrkdp/uut/mem_pos
add wave -noupdate -radix unsigned -childformat {{/l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(5) -radix unsigned} {/l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(4) -radix unsigned} {/l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(3) -radix unsigned} {/l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(2) -radix unsigned} {/l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(1) -radix unsigned} {/l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(0) -radix unsigned}} -subitemconfig {/l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(5) {-height 15 -radix unsigned} /l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(4) {-height 15 -radix unsigned} /l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(3) {-height 15 -radix unsigned} /l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(2) {-height 15 -radix unsigned} /l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(1) {-height 15 -radix unsigned} /l0_rtps_writer_test2_vrkdp/uut/mem_addr_base(0) {-height 15 -radix unsigned}} /l0_rtps_writer_test2_vrkdp/uut/mem_addr_base
add wave -noupdate -childformat {{/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.guid -radix hexadecimal} {/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.addr -radix hexadecimal} {/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.portn -radix hexadecimal} {/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.lease_deadline -radix hexadecimal} {/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.res_time -radix unsigned} {/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.ack_seq_nr_base -radix unsigned} {/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.req_seq_nr_base -radix unsigned}} -expand -subitemconfig {/l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.guid {-height 15 -radix hexadecimal} /l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.addr {-height 15 -radix hexadecimal} /l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.portn {-height 15 -radix hexadecimal} /l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.lease_deadline {-height 15 -radix hexadecimal} /l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.res_time {-height 15 -radix unsigned} /l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.ack_seq_nr_base {-height 15 -radix unsigned} /l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data.req_seq_nr_base {-height 15 -radix unsigned}} /l0_rtps_writer_test2_vrkdp/uut/mem_endpoint_data
add wave -noupdate -group MEM_CTRL -radix unsigned /l0_rtps_writer_test2_vrkdp/uut/mem_addr
add wave -noupdate -group MEM_CTRL /l0_rtps_writer_test2_vrkdp/uut/mem_valid_in
add wave -noupdate -group MEM_CTRL /l0_rtps_writer_test2_vrkdp/uut/mem_ready_in
add wave -noupdate -group MEM_CTRL /l0_rtps_writer_test2_vrkdp/uut/mem_read
add wave -noupdate -group MEM_CTRL -radix hexadecimal /l0_rtps_writer_test2_vrkdp/uut/mem_write_data
add wave -noupdate -group MEM_CTRL /l0_rtps_writer_test2_vrkdp/uut/abort_read
add wave -noupdate -group MEM_CTRL /l0_rtps_writer_test2_vrkdp/uut/mem_valid_out
add wave -noupdate -group MEM_CTRL /l0_rtps_writer_test2_vrkdp/uut/mem_ready_out
add wave -noupdate -group MEM_CTRL -radix hexadecimal /l0_rtps_writer_test2_vrkdp/uut/mem_read_data
add wave -noupdate -divider TESTBENCH
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/start_meta
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/packet_sent_meta
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/start_user
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/packet_sent_user
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/check_trigger
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/mem_check_done
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/stim_done
add wave -noupdate -expand -group TESTBENCH /l0_rtps_writer_test2_vrkdp/test_done
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {Begin {49575000 ps} 1} {Error {7325000 ps} 1} {Cursor {9573934 ps} 0}
quietly wave cursor active 3
configure wave -namecolwidth 150
configure wave -valuecolwidth 135
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {9226708 ps} {10228612 ps}