76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
#ifndef _ALTERA_HPS_0_H_
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#define _ALTERA_HPS_0_H_
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/*
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* This file was automatically generated by the swinfo2header utility.
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*
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* Created from SOPC Builder system 'soc_system' in
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* file './soc_system.sopcinfo'.
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*/
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/*
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* This file contains macros for module 'hps_0' and devices
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* connected to the following masters:
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* h2f_axi_master
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* h2f_lw_axi_master
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*
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* Do not include this header file and another header file created for a
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* different module or master group at the same time.
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* Doing so may result in duplicate macro names.
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* Instead, use the system header file which has macros with unique names.
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*/
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/*
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* Macros for device 'test_fpga_0', class 'test_fpga'
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* The macros are prefixed with 'TEST_FPGA_0_'.
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* The prefix is the slave descriptor.
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*/
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#define TEST_FPGA_0_COMPONENT_TYPE test_fpga
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#define TEST_FPGA_0_COMPONENT_NAME test_fpga_0
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#define TEST_FPGA_0_BASE 0x0
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#define TEST_FPGA_0_SPAN 16
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#define TEST_FPGA_0_END 0xf
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/*
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* Macros for device 'sysid_qsys', class 'altera_avalon_sysid_qsys'
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* The macros are prefixed with 'SYSID_QSYS_'.
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* The prefix is the slave descriptor.
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*/
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#define SYSID_QSYS_COMPONENT_TYPE altera_avalon_sysid_qsys
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#define SYSID_QSYS_COMPONENT_NAME sysid_qsys
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#define SYSID_QSYS_BASE 0x1000
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#define SYSID_QSYS_SPAN 8
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#define SYSID_QSYS_END 0x1007
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#define SYSID_QSYS_ID 2899645186
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#define SYSID_QSYS_TIMESTAMP 1638038262
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/*
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* Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
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* The macros are prefixed with 'JTAG_UART_'.
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* The prefix is the slave descriptor.
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*/
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#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
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#define JTAG_UART_COMPONENT_NAME jtag_uart
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#define JTAG_UART_BASE 0x2000
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#define JTAG_UART_SPAN 8
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#define JTAG_UART_END 0x2007
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#define JTAG_UART_IRQ 2
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#define JTAG_UART_READ_DEPTH 64
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#define JTAG_UART_READ_THRESHOLD 8
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#define JTAG_UART_WRITE_DEPTH 64
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#define JTAG_UART_WRITE_THRESHOLD 8
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/*
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* Macros for device 'ILC', class 'interrupt_latency_counter'
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* The macros are prefixed with 'ILC_'.
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* The prefix is the slave descriptor.
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*/
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#define ILC_COMPONENT_TYPE interrupt_latency_counter
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#define ILC_COMPONENT_NAME ILC
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#define ILC_BASE 0x30000
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#define ILC_SPAN 256
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#define ILC_END 0x300ff
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#endif /* _ALTERA_HPS_0_H_ */
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