John Daktylidis
a1e0297fcb
The Golden Hardware Reference Design (GHRD) is used to implement designs with PS support. The UDP/IP stack of the Linux running on the PS is used to move UDP packets to/from the PL.
75 lines
2.5 KiB
Verilog
75 lines
2.5 KiB
Verilog
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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module debounce (
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clk,
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reset_n,
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data_in,
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data_out
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);
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parameter WIDTH = 32; // set to be the width of the bus being debounced
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parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
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parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
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parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
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input wire clk;
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input wire reset_n;
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input wire [WIDTH-1:0] data_in;
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output wire [WIDTH-1:0] data_out;
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reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
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wire counter_reset [0:WIDTH-1];
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wire counter_enable [0:WIDTH-1];
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// need one counter per input to debounce
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genvar i;
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generate for (i = 0; i < WIDTH; i = i+1)
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begin: debounce_counter_loop
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always @ (posedge clk or negedge reset_n)
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begin
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if (reset_n == 0)
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begin
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counter[i] <= 0;
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end
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else
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begin
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if (counter_reset[i] == 1) // resetting the counter needs to win
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begin
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counter[i] <= 0;
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end
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else if (counter_enable[i] == 1)
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begin
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counter[i] <= counter[i] + 1'b1;
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end
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end
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end
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if (POLARITY == "HIGH")
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begin
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assign counter_reset[i] = (data_in[i] == 0);
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assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
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assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
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end
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else
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begin
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assign counter_reset[i] = (data_in[i] == 1);
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assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
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assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
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end
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end
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endgenerate
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endmodule
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