173 lines
8.6 KiB
Plaintext
173 lines
8.6 KiB
Plaintext
# TCL File Generated by Component Editor 21.1
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# Sat Jul 29 18:35:32 GMT+02:00 2023
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# DO NOT MODIFY
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#
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# test_fpga "test_fpga" v1.0
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# 2023.07.29.18:35:32
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# Test PL-PS Communication
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module test_fpga
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#
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set_module_property DESCRIPTION "Test PL-PS Communication"
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set_module_property NAME test_fpga
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME test_fpga
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
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add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
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add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
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add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
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add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
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add_fileset_file dds_reader.vhd VHDL PATH ../../src/dds_reader.vhd
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add_fileset_file dds_writer.vhd VHDL PATH ../../src/dds_writer.vhd
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add_fileset_file dp_mem_ctrl.vhd VHDL PATH ../../src/dp_mem_ctrl.vhd
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add_fileset_file dual_port_ram.vhd VHDL PATH ../../src/dual_port_ram.vhd
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add_fileset_file dual_port_ram_Altera.vhd VHDL PATH ../../src/dual_port_ram_Altera.vhd
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add_fileset_file dual_port_ram_cfg.vhd VHDL PATH ../../src/dual_port_ram_cfg.vhd
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add_fileset_file mult.vhd VHDL PATH ../../src/mult.vhd
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add_fileset_file mult_Altera.vhd VHDL PATH ../../src/mult_Altera.vhd
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add_fileset_file mult_cfg.vhd VHDL PATH ../../src/mult_cfg.vhd
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add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
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add_fileset_file rtps_discovery_module.vhd VHDL PATH ../../src/rtps_discovery_module.vhd
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add_fileset_file rtps_handler.vhd VHDL PATH ../../src/rtps_handler.vhd
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add_fileset_file rtps_out.vhd VHDL PATH ../../src/rtps_out.vhd
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add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
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add_fileset_file rtps_reader.vhd VHDL PATH ../../src/rtps_reader.vhd
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add_fileset_file rtps_writer.vhd VHDL PATH ../../src/rtps_writer.vhd
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add_fileset_file single_port_ram.vhd VHDL PATH ../../src/single_port_ram.vhd
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add_fileset_file single_port_ram_Altera.vhd VHDL PATH ../../src/single_port_ram_Altera.vhd
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add_fileset_file single_port_ram_cfg.vhd VHDL PATH ../../src/single_port_ram_cfg.vhd
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add_fileset_file vector_FIFO.vhd VHDL PATH ../../src/vector_FIFO.vhd
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add_fileset_file dds_user_config.vhd VHDL PATH ../../src/ros2/dds_user_config.vhd
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add_fileset_file ros_action_server.vhd VHDL PATH ../../src/ros2/ros_action_server.vhd
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add_fileset_file ros_config_package.vhd VHDL PATH ../../src/ros2/ros_config_package.vhd
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add_fileset_file ros_package.vhd VHDL PATH ../../src/ros2/ros_package.vhd
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add_fileset_file ros_static_discovery_writer.vhd VHDL PATH ../../src/ros2/ros_static_discovery_writer.vhd
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add_fileset_file ros_time_converter.vhd VHDL PATH ../../src/ros2/ros_time_converter.vhd
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add_fileset_file CancelGoal_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_package.vhd
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add_fileset_file CancelGoal_ros_srv_client.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_client.vhd
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add_fileset_file CancelGoal_ros_srv_server.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/CancelGoal_ros_srv_server.vhd
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add_fileset_file GoalInfo_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalInfo_package.vhd
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add_fileset_file GoalStatusArray_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_package.vhd
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add_fileset_file GoalStatusArray_ros_pub.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_pub.vhd
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add_fileset_file GoalStatusArray_ros_sub.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatusArray_ros_sub.vhd
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add_fileset_file GoalStatus_package.vhd VHDL PATH ../../src/ros2/rcl_interfaces/action_msgs/GoalStatus_package.vhd
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add_fileset_file Fibonacci_package.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_package.vhd
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add_fileset_file Fibonacci_ros_action_client.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_client.vhd
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add_fileset_file Fibonacci_ros_action_feedback_pub.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_feedback_pub.vhd
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add_fileset_file Fibonacci_ros_action_feedback_sub.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_feedback_sub.vhd
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add_fileset_file Fibonacci_ros_action_goal_srv_client.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_goal_srv_client.vhd
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add_fileset_file Fibonacci_ros_action_goal_srv_server.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_goal_srv_server.vhd
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add_fileset_file Fibonacci_ros_action_result_srv_client.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_client.vhd
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add_fileset_file Fibonacci_ros_action_result_srv_server.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_result_srv_server.vhd
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add_fileset_file Fibonacci_ros_action_server.vhd VHDL PATH ../../src/ros2/example_interfaces/Fibonacci_ros_action_server.vhd
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add_fileset_file Fibonacci.vhd VHDL PATH ../../src/ros2/Tests/Fibonacci.vhd
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add_fileset_file L2_Testbench_ROS_Lib4.vhd VHDL PATH ../../src/ros2/Tests/Level_2/L2_Testbench_ROS_Lib4.vhd
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add_fileset_file syn_ros_action_config.vhd VHDL PATH ../syn_ros_action_config.vhd
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add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
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add_fileset_file mem_ctrl.vhd VHDL PATH ../../src/mem_ctrl.vhd
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset reset Input 1
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#
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# connection point avalon_slave_0
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#
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add_interface avalon_slave_0 avalon end
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set_interface_property avalon_slave_0 addressUnits WORDS
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set_interface_property avalon_slave_0 associatedClock clock
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set_interface_property avalon_slave_0 associatedReset reset
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set_interface_property avalon_slave_0 bitsPerSymbol 8
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set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave_0 burstcountUnits WORDS
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set_interface_property avalon_slave_0 explicitAddressSpan 0
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set_interface_property avalon_slave_0 holdTime 0
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set_interface_property avalon_slave_0 linewrapBursts false
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set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
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set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
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set_interface_property avalon_slave_0 readLatency 0
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set_interface_property avalon_slave_0 readWaitTime 1
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set_interface_property avalon_slave_0 setupTime 0
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set_interface_property avalon_slave_0 timingUnits Cycles
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set_interface_property avalon_slave_0 writeWaitTime 0
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set_interface_property avalon_slave_0 ENABLED true
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set_interface_property avalon_slave_0 EXPORT_OF ""
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set_interface_property avalon_slave_0 PORT_NAME_MAP ""
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set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave_0 address address Input 2
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add_interface_port avalon_slave_0 read read Input 1
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add_interface_port avalon_slave_0 write write Input 1
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add_interface_port avalon_slave_0 readdata readdata Output 32
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add_interface_port avalon_slave_0 writedata writedata Input 32
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add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
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