f96af25a6a
Test RTPS Output (DATA and GAP Message Generation) of the RTPS Writer. Backport some small changes to Test1. Compiling and Passing
99 lines
8.4 KiB
Plaintext
99 lines
8.4 KiB
Plaintext
onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider SYSTEM
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/clk
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/reset
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add wave -noupdate -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/time
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add wave -noupdate -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/check_time
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add wave -noupdate -divider INPUT
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add wave -noupdate -group META /l1_rtps_writer_test1_vrkdp/uut/empty_meta
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add wave -noupdate -group META /l1_rtps_writer_test1_vrkdp/uut/rd_meta
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add wave -noupdate -group META /l1_rtps_writer_test1_vrkdp/uut/last_word_in_meta
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add wave -noupdate -group META -radix hexadecimal /l1_rtps_writer_test1_vrkdp/uut/data_in_meta
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add wave -noupdate -group USER /l1_rtps_writer_test1_vrkdp/uut/empty_user
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add wave -noupdate -group USER /l1_rtps_writer_test1_vrkdp/uut/rd_user
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add wave -noupdate -group USER -radix hexadecimal /l1_rtps_writer_test1_vrkdp/uut/data_in_user
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add wave -noupdate -group USER /l1_rtps_writer_test1_vrkdp/uut/last_word_in_user
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add wave -noupdate -divider HC
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/data_available
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/start_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/opcode_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/ack_hc
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add wave -noupdate -expand -group HC -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/seq_nr_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/done_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/ret_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/get_data_hc
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add wave -noupdate -expand -group HC -radix hexadecimal /l1_rtps_writer_test1_vrkdp/uut/data_in_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/valid_in_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/ready_in_hc
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/last_word_in_hc
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add wave -noupdate -expand -group HC -radix hexadecimal /l1_rtps_writer_test1_vrkdp/uut/cc_instance_handle
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add wave -noupdate -expand -group HC /l1_rtps_writer_test1_vrkdp/uut/cc_kind
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add wave -noupdate -expand -group HC -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/cc_source_timestamp
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add wave -noupdate -expand -group HC -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/cc_seq_nr
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add wave -noupdate -divider OUTPUT
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/full_rtps
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/wr_rtps
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add wave -noupdate -radix hexadecimal /l1_rtps_writer_test1_vrkdp/uut/data_out_rtps
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/last_word_out_rtps
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/rtps_out_inst/wr
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add wave -noupdate -radix hexadecimal /l1_rtps_writer_test1_vrkdp/rtps_out_inst/data_out
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add wave -noupdate -divider {MAIN FSM}
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/stage
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/stage_next
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/cnt
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add wave -noupdate -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/last_seq_nr
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add wave -noupdate -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/global_ack_seq_nr_base
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add wave -noupdate -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/next_seq_nr
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add wave -noupdate -divider {MEMORY FSM}
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/mem_op_done
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/mem_op_start
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/mem_opcode
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/mem_stage
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/mem_stage_next
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/mem_cnt
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/mem_pos
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add wave -noupdate -radix unsigned -childformat {{/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(6) -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(5) -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(4) -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(3) -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(2) -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(1) -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(0) -radix unsigned}} -subitemconfig {/l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(6) {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(5) {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(4) {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(3) {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(2) {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(1) {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_addr_base(0) {-height 15 -radix unsigned}} /l1_rtps_writer_test1_vrkdp/uut/mem_addr_base
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add wave -noupdate -childformat {{/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.guid -radix hexadecimal} {/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.addr -radix hexadecimal} {/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.portn -radix hexadecimal} {/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.lease_deadline -radix hexadecimal} {/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.res_time -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.ack_seq_nr_base -radix unsigned} {/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.req_seq_nr_base -radix unsigned}} -expand -subitemconfig {/l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.guid {-height 15 -radix hexadecimal} /l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.addr {-height 15 -radix hexadecimal} /l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.portn {-height 15 -radix hexadecimal} /l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.lease_deadline {-height 15 -radix hexadecimal} /l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.res_time {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.ack_seq_nr_base {-height 15 -radix unsigned} /l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data.req_seq_nr_base {-height 15 -radix unsigned}} /l1_rtps_writer_test1_vrkdp/uut/mem_endpoint_data
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add wave -noupdate -group MEM_CTRL -radix unsigned /l1_rtps_writer_test1_vrkdp/uut/mem_addr
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add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test1_vrkdp/uut/mem_valid_in
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add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test1_vrkdp/uut/mem_ready_in
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add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test1_vrkdp/uut/mem_read
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add wave -noupdate -group MEM_CTRL -radix hexadecimal /l1_rtps_writer_test1_vrkdp/uut/mem_write_data
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add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test1_vrkdp/uut/abort_read
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add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test1_vrkdp/uut/mem_valid_out
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add wave -noupdate -group MEM_CTRL /l1_rtps_writer_test1_vrkdp/uut/mem_ready_out
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add wave -noupdate -group MEM_CTRL -radix hexadecimal /l1_rtps_writer_test1_vrkdp/uut/mem_read_data
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add wave -noupdate -divider TESTBENCH
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/start_meta
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/packet_sent_meta
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/start_user
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/packet_sent_user
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/stage_hc
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/out_check_done
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/stim_done
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add wave -noupdate -group TESTBENCH /l1_rtps_writer_test1_vrkdp/test_done
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add wave -noupdate -divider MISC
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/req_bitmap_pos
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/req_seq_nr_bitmap
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/nack_bitmap_pos
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add wave -noupdate /l1_rtps_writer_test1_vrkdp/uut/bitmap_latch
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {Begin {49575000 ps} 1} {Error {7325000 ps} 1} {Cursor {62689107 ps} 0}
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quietly wave cursor active 3
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 135
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {61771800 ps} {62773704 ps}
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