b47d409f13
Remove non-Quartus-supported VHDL 2008 features. Remove inferred Latches. Add test Entities to see resulting hw synthesis of various code segments.
37 lines
873 B
VHDL
37 lines
873 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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-- Test synthesis of array indexing
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entity test5 is
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port (
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clk : in std_logic;
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reset : in std_logic;
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input : in std_logic_vector(31 downto 0);
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input2 : in std_logic_vector(31 downto 0);
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output : out std_logic_vector(7 downto 0)
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);
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end entity;
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architecture arch of test5 is
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begin
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process (all)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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output <= (others => '0');
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else
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output <= get_sub_vector(input, to_integer(unsigned(input2(1 downto 0))), 8, TRUE);
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end if;
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end if;
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end process;
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end architecture;
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