95 lines
2.9 KiB
VHDL
95 lines
2.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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entity test_top is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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-- AVALON MM INTERFACE
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address : in std_logic_vector(1 downto 0);
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read : in std_logic;
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write : in std_logic;
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readdata : out std_logic_vector(WORD_WIDTH-1 downto 0);
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writedata : in std_logic_vector(WORD_WIDTH-1 downto 0);
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waitrequest : out std_logic
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);
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end entity;
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architecture arch of test_top is
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signal full_fi_wr, write_wr_fi, empty_fo_wr, read_wr_fo, empty_fi_test, read_test_fi, full_fo_test, write_test_fo : std_logic;
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signal data_wr_fi, data_fo_wr, data_fi_test, data_test_fo : std_logic_vector(WORD_WIDTH-1 downto 0);
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begin
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Avalon_MM_wrapper_inst : entity work.Avalon_MM_wrapper(arch)
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port map (
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clk => clk,
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reset => reset,
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address => address,
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read => read,
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write => write,
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readdata => readdata,
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writedata => writedata,
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waitrequest => waitrequest,
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full_ri => full_fi_wr,
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write_ri => write_wr_fi,
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data_ri => data_wr_fi,
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empty_ro => empty_fo_wr,
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read_ro => read_wr_fo,
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data_ro => data_fo_wr
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);
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FIFO_IN_inst : configuration work.FWFT_FIFO_cfg
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generic map (
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FIFO_DEPTH => 16384,
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DATA_WIDTH => 32
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)
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port map (
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clk => clk,
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reset => reset,
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data_in => data_wr_fi,
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write => write_wr_fi,
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read => read_test_fi,
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data_out => data_fi_test,
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empty => empty_fi_test,
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full => full_fi_wr,
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free => open
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);
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FIFO_OUT_inst : configuration work.FWFT_FIFO_cfg
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generic map (
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FIFO_DEPTH => 16384,
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DATA_WIDTH => 32
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)
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port map (
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clk => clk,
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reset => reset,
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data_in => data_test_fo,
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write => write_test_fo,
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read => read_wr_fo,
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data_out => data_fo_wr,
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empty => empty_fo_wr,
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full => full_fo_test,
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free => open
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);
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test_fpga_inst : entity work.test_fpga(arch)
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port map (
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clk => clk,
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reset => reset,
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empty => empty_fi_test,
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read => read_test_fi,
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data_in => data_fi_test,
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full => full_fo_test,
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write => write_test_fo,
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data_out => data_test_fo
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);
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end architecture;
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