0f50e66942
* Added rtps_builtin_endpoint_test7 Level 1 testbench - Compiling and Passing * Various Bug Fixes in rtps_builtin_endpoint
67 lines
2.2 KiB
VHDL
67 lines
2.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity FWFT_FIFO is
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generic(
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FIFO_DEPTH : natural := 2;
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DATA_WIDTH : natural := 32
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);
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port
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(
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reset : in std_logic;
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clk : in std_logic;
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data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
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write : in std_logic;
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read : in std_logic;
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data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
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empty : out std_logic;
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full : out std_logic;
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free : out natural range 0 to FIFO_DEPTH
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);
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end entity;
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architecture arch of FWFT_FIFO is
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-- *TYPE DECLARATIONS*
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type FIFO_DATA_ARRAY is array (FIFO_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
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-- *SIGNAL DECLARATIONS*
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signal fifo_data : FIFO_DATA_ARRAY := (others => (others => '0'));
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signal free_sig : natural range 0 to FIFO_DEPTH := FIFO_DEPTH;
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begin
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data_out <= fifo_data(0);
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free <= free_sig;
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empty <= '1' when (free_sig = FIFO_DEPTH) else '0';
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full <= '1' when (free_sig = 0) else '0';
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sync : process(clk, reset)
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variable free_var : integer range 0 to FIFO_DEPTH;
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begin
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if(rising_edge(clk)) then
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if(reset = '1') then
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fifo_data <= (others => (others => '0'));
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free_sig <= FIFO_DEPTH;
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else
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free_var := free_sig;
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if(read = '1' and free_var < FIFO_DEPTH ) then
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for i in 1 to (FIFO_DEPTH-1) loop
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fifo_data(i-1) <= fifo_data(i);
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end loop;
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fifo_data(FIFO_DEPTH-1) <= (others => '0');
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free_var := free_var + 1;
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end if;
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if(write = '1') then
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if(free_var > 0) then
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fifo_data(FIFO_DEPTH-free_var) <= data_in;
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free_var := free_var - 1;
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end if;
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end if;
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free_sig <= free_var;
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end if;
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end if;
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end process;
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end architecture; |