260acba5b6
Test Liveliness Handling of RTPS Reader. Test 2 expanded with extra case for Little Endian Handling. Compiling and Passing
660 lines
25 KiB
VHDL
660 lines
25 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm; -- Utility Library
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context osvvm.OsvvmContext;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.rtps_test_package.all;
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-- This testbench tests the Liveliness handling of the RTPS Reader.
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-- The testbench checks the memory contents at specific times, and also checks if the removal is propagated to the History Cache.
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entity L0_rtps_reader_test3_m is
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end entity;
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architecture testbench of L0_rtps_reader_test3_m is
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-- *CONSTANT DECLARATION*
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constant MAX_REMOTE_ENDPOINTS : natural := 3;
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constant ACCEPT_RES : std_logic_vector(WORD_WIDTH downto 0) := (others => '0');
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constant REJECT_RES : std_logic_vector(WORD_WIDTH downto 0) := (others => '1');
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-- *TYPE DECLARATION*
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type SEND_STAGE_TYPE is (IDLE, BUSY);
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type CHECK_STAGE_TYPE is (IDLE, CHECK, RESPONSE);
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type TEST_RAM_TYPE is array (0 to (MAX_REMOTE_ENDPOINTS*WRITER_ENDPOINT_FRAME_SIZE_A)-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
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-- *SIGNAL DECLARATION*
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signal clk, empty_user, empty_meta, rd_user, rd_meta, last_word_in_user, last_word_in_meta : std_logic := '0';
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signal reset : std_logic := '1';
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signal data_in_user, data_in_meta, data_out_hc : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal start_hc, ack_hc, done_hc, done_hc_delay, ready_out_hc, valid_out_hc, last_word_out_hc : std_logic := '0';
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signal opcode_hc : HISTORY_CACHE_OPCODE_TYPE := NOP;
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signal ret_hc : HISTORY_CACHE_RESPONSE_TYPE := OK;
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signal test_time : TIME_TYPE := TIME_INVALID;
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signal stim_stage_user, stim_stage_meta : SEND_STAGE_TYPE := IDLE;
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signal check_stage : CHECK_STAGE_TYPE := IDLE;
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shared variable stimulus_user, stimulus_meta, reference : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
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signal packet_sent_user, packet_sent_meta : std_logic := '0';
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signal cnt_stim_meta, cnt_stim_user : natural := 0;
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signal start_meta, start_user : std_logic := '0';
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shared variable SB_out : osvvm.ScoreBoardPkg_slv.ScoreBoardPType;
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shared variable SB_mem : work.ScoreBoardPkg_MemoryTest.ScoreBoardPType;
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signal stim_done, mem_check_done, out_check_done, test_done, mem_check : std_logic := '0';
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-- *FUNCTION DECLARATION*
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function gen_sn(input : natural) return SEQUENCENUMBER_TYPE is
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variable ret : SEQUENCENUMBER_TYPE;
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begin
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ret(0) := (others => '0');
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ret(1) := unsigned(int(input, WORD_WIDTH));
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return ret;
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end function;
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begin
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-- Unit Under Test
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uut : entity work.rtps_reader(arch)
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generic map (
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ENTITYID => DEFAULT_READER_ENTITYID,
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RELIABILTY_QOS => RELIABLE_RELIABILITY_QOS,
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LIVELINESS_QOS => MANUAL_BY_TOPIC_LIVELINESS_QOS,
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DURABILITY_QOS => VOLATILE_DURABILITY_QOS,
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HEARTBEAT_RESPONSE_DELAY => DURATION_ZERO,
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HEARTBEAT_SUPPRESSION_DELAY => DURATION_ZERO,
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LEASE_DURATION => gen_duration(5,0),
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WITH_KEY => TRUE,
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MAX_REMOTE_ENDPOINTS => MAX_REMOTE_ENDPOINTS
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)
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port map (
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-- SYSTEM
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clk => clk,
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reset => reset,
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time => test_time,
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empty_user => empty_user or packet_sent_user,
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rd_user => rd_user,
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data_in_user => data_in_user,
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last_word_in_user => last_word_in_user,
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empty_meta => empty_meta or packet_sent_meta,
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rd_meta => rd_meta,
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data_in_meta => data_in_meta,
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last_word_in_meta => last_word_in_meta,
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wr_rtps => open,
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full_rtps => '0',
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last_word_out_rtps => open,
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data_out_rtps => open,
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start_hc => start_hc,
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opcode_hc => opcode_hc,
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ack_hc => ack_hc,
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done_hc => done_hc,
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ret_hc => ret_hc,
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data_out_hc => data_out_hc,
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valid_out_hc => valid_out_hc,
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ready_out_hc => ready_out_hc,
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last_word_out_hc => last_word_out_hc
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);
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stimulus_prc : process
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variable RV : RandomPType;
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variable p0, p1, p2 : PARTICIPANT_DATA_TYPE := DEFAULT_PARTICIPANT_DATA;
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variable e0, e1, e2, endpoint : ENDPOINT_DATA_TYPE := DEFAULT_ENDPOINT_DATA;
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variable payload : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
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variable sub : RTPS_SUBMESSAGE_TYPE := DEFAULT_RTPS_SUBMESSAGE;
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variable cc : CACHE_CHANGE_TYPE := DEFAULT_CACHE_CHANGE;
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alias mem_op_done is <<signal uut.mem_op_done : std_logic>>;
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alias idle_sig is <<signal uut.idle_sig : std_logic>>;
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-- Wrapper to use procedure as function
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impure function gen_rand_loc_2 return LOCATOR_TYPE is
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variable ret : LOCATOR_TYPE := EMPTY_LOCATOR;
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begin
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gen_rand_loc(RV, ret);
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return ret;
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end function;
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impure function gen_rand_guid_prefix return GUIDPREFIX_TYPE is
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variable ret : GUIDPREFIX_TYPE;
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begin
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ret := (0 => RV.RandSlv(WORD_WIDTH), 1 => RV.RandSlv(WORD_WIDTH), 2 => RV.RandSlv(WORD_WIDTH));
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return ret;
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end function;
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procedure start_meta_test is
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begin
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start_meta <= '1';
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wait until rising_edge(clk);
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start_meta <= '0';
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wait until rising_edge(clk);
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end procedure;
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procedure start_user_test is
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begin
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start_user <= '1';
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wait until rising_edge(clk);
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start_user <= '0';
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wait until rising_edge(clk);
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end procedure;
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procedure push_reference(accept : in BOOLEAN) is
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begin
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-- NOTE: First Word represents the Response that we will return.
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if (accept) then
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SB_out.Push(ACCEPT_RES);
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else
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SB_out.Push(REJECT_RES);
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end if;
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for i in 0 to reference.length-1 loop
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SB_out.Push(reference.last(i) & reference.data(i));
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end loop;
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end procedure;
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impure function gen_payload return TEST_PACKET_TYPE is
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variable ret : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
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begin
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for i in 0 to RV.RandInt(1,10) loop
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ret.data(ret.length) := RV.RandSlv(WORD_WIDTH);
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ret.length := ret.length + 1;
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end loop;
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return ret;
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end function;
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impure function gen_key_hash return KEY_HASH_TYPE is
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variable ret : KEY_HASH_TYPE := (others => (others => '0'));
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begin
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for i in 0 to KEY_HASH_TYPE'length-1 loop
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ret(i) := RV.RandSlv(WORD_WIDTH);
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end loop;
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return ret;
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end function;
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procedure wait_on_meta_sent is
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begin
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wait until rising_edge(packet_sent_meta);
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end procedure;
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procedure wait_on_user_sent is
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begin
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wait until rising_edge(packet_sent_user);
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end procedure;
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procedure wait_on_out_check is
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begin
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if (out_check_done /= '1') then
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wait until out_check_done = '1';
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end if;
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end procedure;
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procedure wait_on_mem_check is
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begin
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if (mem_check_done /= '1') then
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wait until mem_check_done = '1';
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end if;
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end procedure;
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procedure wait_on_completion is
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begin
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if (test_done /= '1') then
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wait until test_done = '1';
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end if;
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end procedure;
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procedure wait_on_idle is
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begin
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if (idle_sig /= '1' or mem_op_done /= '1') then
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wait until idle_sig = '1' and mem_op_done = '1';
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end if;
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end procedure;
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begin
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SetAlertLogName("rtps_reader - (Manual by Topic Liveliness) - Level 0 - Liveliness Handling");
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SetAlertEnable(FAILURE, TRUE);
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SetAlertEnable(ERROR, TRUE);
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SetAlertEnable(WARNING, TRUE);
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SetLogEnable(DEBUG, FALSE);
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SetLogEnable(PASSED, FALSE);
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SetLogEnable(INFO, TRUE);
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RV.InitSeed(RV'instance_name);
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-- Participant 0
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p0 := DEFAULT_PARTICIPANT_DATA;
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p0.guidPrefix := gen_rand_guid_prefix;
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-- Participant 1
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p1 := DEFAULT_PARTICIPANT_DATA;
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p1.guidPrefix := gen_rand_guid_prefix;
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-- Participant 2
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p2 := DEFAULT_PARTICIPANT_DATA;
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p2.guidPrefix := gen_rand_guid_prefix;
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-- Endpoint 1
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e0 := DEFAULT_ENDPOINT_DATA;
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e0.entityid := RV.RandSlv(ENTITYID_WIDTH);
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e0.participant := p0;
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e0.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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-- Endpoint 2
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e1 := DEFAULT_ENDPOINT_DATA;
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e1.entityid := RV.RandSlv(ENTITYID_WIDTH);
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e1.participant := p1;
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e1.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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-- Endpoint 3
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e2 := DEFAULT_ENDPOINT_DATA;
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e2.entityid := RV.RandSlv(ENTITYID_WIDTH);
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e2.participant := p2;
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e2.unicastLocatorList := (numLocators => int(1,CDR_LONG_WIDTH), locator => (0 => gen_rand_loc_2, others => EMPTY_LOCATOR));
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Log("Initiating Test", INFO);
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test_time <= TIME_ZERO;
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stim_done <= '0';
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start_meta <= '0';
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start_user <= '0';
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mem_check <= '0';
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reset <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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reset <= '0';
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Log("Current Time: 0 s", INFO);
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wait until rising_edge(clk);
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Log("Insert Endpoint 0 Participant 0", INFO);
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endpoint := e0;
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endpoint.nr := 0;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus_meta);
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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start_meta_test;
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wait_on_meta_sent;
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mem_check <= '1';
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wait_on_mem_check;
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mem_check <= '0';
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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Log("Insert Endpoint 1 Participant 1", INFO);
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endpoint := e1;
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endpoint.nr := 1;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus_meta);
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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start_meta_test;
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wait_on_meta_sent;
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mem_check <= '1';
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wait_on_mem_check;
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mem_check <= '0';
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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Log("Insert Endpoint 2 Participant 2", INFO);
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endpoint := e2;
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endpoint.nr := 2;
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endpoint.match := MATCH;
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gen_endpoint_match_frame(endpoint, stimulus_meta);
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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start_meta_test;
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wait_on_meta_sent;
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mem_check <= '1';
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wait_on_mem_check;
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mem_check <= '0';
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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wait_on_idle;
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Log("Current Time: 1 s", INFO);
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test_time <= gen_duration(1,0);
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wait until rising_edge(clk);
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Log("Accept Endpoint 0 sent DATA [SN 1]", INFO);
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endpoint := e0;
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sub := DEFAULT_RTPS_SUBMESSAGE;
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sub.submessageID := SID_DATA;
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sub.writerId := endpoint.entityid;
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sub.readerId := DEFAULT_READER_ENTITYID;
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sub.writerSN := gen_sn(1);
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sub.flags(SUBMESSAGE_DATA_FLAG_POS) := '1';
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sub.data := gen_payload;
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gen_rtps_handler_out(sub, get_loc(endpoint), FALSE, TIME_INVALID, endpoint.participant.guidPrefix, stimulus_user);
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cc := gen_cache_change(sub);
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gen_add_cache_change_dds(cc, TIME_INVALID, endpoint.nr, reference);
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push_reference(TRUE);
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start_user_test;
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wait_on_user_sent;
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wait_on_out_check;
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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wait_on_idle;
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Log("Current Time: 2 s", INFO);
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test_time <= gen_duration(2,0);
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wait until rising_edge(clk);
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Log("Participant 1 Liveliness Update [Ignored]", INFO);
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gen_liveliness_update_frame(p1, stimulus_meta);
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start_meta_test;
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wait_on_meta_sent;
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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wait_on_idle;
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Log("Current Time: 3 s", INFO);
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test_time <= gen_duration(3,0);
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wait until rising_edge(clk);
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Log("Endpoint 2 HEARTBEAT Liveliness Update", INFO);
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endpoint := e2;
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sub := DEFAULT_RTPS_SUBMESSAGE;
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sub.submessageID := SID_HEARTBEAT;
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sub.writerId := endpoint.entityid;
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sub.readerId := DEFAULT_READER_ENTITYID;
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sub.firstSN := gen_sn(0);
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sub.lastSN := gen_sn(1);
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sub.flags(SUBMESSAGE_LIVELINESS_FLAG_POS) := '1';
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gen_rtps_handler_out(sub, get_loc(endpoint), FALSE, TIME_INVALID, endpoint.participant.guidPrefix, stimulus_user);
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start_user_test;
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wait_on_user_sent;
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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wait_on_idle;
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Log("Current Time: 5 s", INFO);
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test_time <= gen_duration(5,0);
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wait until rising_edge(clk);
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Log("Check removal of Endpoint 1", INFO);
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endpoint := e0;
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endpoint.nr := 0;
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endpoint.match := MATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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endpoint := e1;
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endpoint.nr := 1;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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endpoint := e2;
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endpoint.nr := 2;
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endpoint.match := MATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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SB_out.Push("0" & std_logic_vector(to_unsigned(1, WORD_WIDTH)));
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wait_on_out_check;
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mem_check <= '1';
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wait_on_mem_check;
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mem_check <= '0';
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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wait_on_idle;
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Log("Current Time: 6 s", INFO);
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test_time <= gen_duration(6,0);
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wait until rising_edge(clk);
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Log("Check removal of Endpoint 0", INFO);
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endpoint := e0;
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endpoint.nr := 0;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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endpoint := e1;
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endpoint.nr := 1;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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endpoint := e2;
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endpoint.nr := 2;
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endpoint.match := MATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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SB_out.Push("0" & std_logic_vector(to_unsigned(0, WORD_WIDTH)));
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wait_on_out_check;
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mem_check <= '1';
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wait_on_mem_check;
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mem_check <= '0';
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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wait_on_idle;
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Log("Current Time: 8 s", INFO);
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test_time <= gen_duration(8,0);
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wait until rising_edge(clk);
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Log("Check removal of Endpoint 1", INFO);
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endpoint := e0;
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endpoint.nr := 0;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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endpoint := e1;
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endpoint.nr := 1;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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endpoint := e2;
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endpoint.nr := 2;
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endpoint.match := UNMATCH;
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SB_mem.Push(gen_writer_endpoint_mem_frame_a(endpoint));
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SB_out.Push("0" & std_logic_vector(to_unsigned(2, WORD_WIDTH)));
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wait_on_out_check;
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mem_check <= '1';
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wait_on_mem_check;
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mem_check <= '0';
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stimulus_meta := EMPTY_TEST_PACKET;
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stimulus_user := EMPTY_TEST_PACKET;
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reference := EMPTY_TEST_PACKET;
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stim_done <= '1';
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wait_on_completion;
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TranscriptOpen(RESULTS_FILE, APPEND_MODE);
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SetTranscriptMirror;
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ReportAlerts;
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TranscriptClose;
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std.env.stop;
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wait;
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end process;
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clock_prc : process
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begin
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clk <= '0';
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wait for 25 ns;
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|
clk <= '1';
|
|
wait for 25 ns;
|
|
end process;
|
|
|
|
empty_meta_prc : process
|
|
begin
|
|
empty_meta <= '0';
|
|
wait until rd_meta = '1';
|
|
wait until rising_edge(clk);
|
|
empty_meta <= '1';
|
|
wait until rising_edge(clk);
|
|
end process;
|
|
|
|
empty_user_prc : process
|
|
begin
|
|
empty_user <= '0';
|
|
wait until rd_user = '1';
|
|
wait until rising_edge(clk);
|
|
empty_user <= '1';
|
|
wait until rising_edge(clk);
|
|
end process;
|
|
|
|
alert_prc : process(all)
|
|
begin
|
|
if rising_edge(clk) then
|
|
alertif(empty_meta = '1' and rd_meta = '1', "Input FIFO read signal high while empty signal high (meta)", ERROR);
|
|
alertif(empty_user = '1' and rd_user = '1', "Input FIFO read signal high while empty signal high (user)", ERROR);
|
|
end if;
|
|
end process;
|
|
|
|
input_meta_prc : process(all)
|
|
begin
|
|
data_in_meta <= stimulus_meta.data(cnt_stim_meta);
|
|
last_word_in_meta <= stimulus_meta.last(cnt_stim_meta);
|
|
|
|
if rising_edge(clk) then
|
|
if (reset = '1') then
|
|
cnt_stim_meta <= 0;
|
|
stim_stage_meta <= IDLE;
|
|
packet_sent_meta <= '1';
|
|
else
|
|
case (stim_stage_meta) is
|
|
when IDLE =>
|
|
if (start_meta = '1' and stimulus_meta.length /= 0) then
|
|
stim_stage_meta <= BUSY;
|
|
packet_sent_meta <= '0';
|
|
end if;
|
|
when BUSY =>
|
|
if (rd_meta = '1') then
|
|
if (cnt_stim_meta = stimulus_meta.length-1) then
|
|
stim_stage_meta <= IDLE;
|
|
packet_sent_meta <= '1';
|
|
cnt_stim_meta <= 0;
|
|
else
|
|
cnt_stim_meta <= cnt_stim_meta + 1;
|
|
end if;
|
|
end if;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
input_user_prc : process(all)
|
|
begin
|
|
data_in_user <= stimulus_user.data(cnt_stim_user);
|
|
last_word_in_user <= stimulus_user.last(cnt_stim_user);
|
|
|
|
if rising_edge(clk) then
|
|
if (reset = '1') then
|
|
cnt_stim_user <= 0;
|
|
stim_stage_user <= IDLE;
|
|
packet_sent_user <= '1';
|
|
else
|
|
case (stim_stage_user) is
|
|
when IDLE =>
|
|
if (start_user = '1' and stimulus_user.length /= 0) then
|
|
stim_stage_user <= BUSY;
|
|
packet_sent_user <= '0';
|
|
end if;
|
|
when BUSY =>
|
|
if (rd_user = '1') then
|
|
if (cnt_stim_user = stimulus_user.length-1) then
|
|
stim_stage_user <= IDLE;
|
|
packet_sent_user <= '1';
|
|
cnt_stim_user <= 0;
|
|
else
|
|
cnt_stim_user <= cnt_stim_user + 1;
|
|
end if;
|
|
end if;
|
|
end case;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
done_proc : process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if (stim_done = '1' and SB_out.empty) then
|
|
test_done <= '1';
|
|
else
|
|
test_done <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
out_check_prc : process(all)
|
|
variable accept : std_logic_vector(WORD_WIDTH downto 0);
|
|
begin
|
|
if rising_edge(clk) then
|
|
case (check_stage) is
|
|
when IDLE =>
|
|
ack_hc <= '0';
|
|
done_hc <= '0';
|
|
ready_out_hc <= '0';
|
|
ret_hc <= ERROR;
|
|
out_check_done <= '0';
|
|
if (start_hc = '1') then
|
|
ack_hc <= '1';
|
|
check_stage <= CHECK;
|
|
case (opcode_hc) is
|
|
when REMOVE_WRITER =>
|
|
SB_out.Check(last_word_out_hc & data_out_hc);
|
|
accept := ACCEPT_RES;
|
|
check_stage <= RESPONSE;
|
|
when ADD_CACHE_CHANGE =>
|
|
-- Pop Response Value
|
|
SB_out.pop(accept);
|
|
when others =>
|
|
Alert("Unexpected HC Opcode", ERROR);
|
|
end case;
|
|
end if;
|
|
when CHECK =>
|
|
ack_hc <= '0';
|
|
ready_out_hc <= '1';
|
|
out_check_done <= '0';
|
|
if (valid_out_hc = '1') then
|
|
SB_out.Check(last_word_out_hc & data_out_hc);
|
|
|
|
if (last_word_out_hc = '1') then
|
|
ready_out_hc <= '0';
|
|
check_stage <= RESPONSE;
|
|
end if;
|
|
end if;
|
|
when RESPONSE =>
|
|
ack_hc <= '0';
|
|
ready_out_hc <= '0';
|
|
done_hc <= '1';
|
|
if (accept = ACCEPT_RES) then
|
|
ret_hc <= OK;
|
|
else
|
|
ret_hc <= REJECTED;
|
|
end if;
|
|
check_stage <= IDLE;
|
|
out_check_done <= '1';
|
|
end case;
|
|
end if;
|
|
end process;
|
|
|
|
mem_check_prc : process
|
|
alias mem is <<signal uut.mem_ctrl_inst.ram_inst.mem : TEST_RAM_TYPE>>;
|
|
alias mem_op_done is <<signal uut.mem_op_done : std_logic>>;
|
|
alias idle_sig is <<signal uut.idle_sig : std_logic>>;
|
|
variable reference : TEST_WRITER_ENDPOINT_MEMORY_FRAME_TYPE_A;
|
|
begin
|
|
mem_check_done <= '0';
|
|
-- SAFEGUARD: (Prevent Fall-through Behavior)
|
|
if (reset /= '0') then
|
|
wait until reset = '0';
|
|
end if;
|
|
-- Wait for Stimulus Process to give the go
|
|
wait until rising_edge(mem_check);
|
|
-- Wait for UUT IDLE state
|
|
if (idle_sig /= '1') then
|
|
wait until idle_sig = '1';
|
|
end if;
|
|
-- Wait for ongoing memory operation
|
|
if (mem_op_done /= '1') then
|
|
wait until mem_op_done = '1';
|
|
end if;
|
|
while (not SB_mem.empty) loop
|
|
SB_mem.Pop(reference);
|
|
for i in 0 to reference'length-1 loop
|
|
AffirmIf(?? (mem(reference(i).addr) ?= reference(i).data), "Address: " & integer'image(reference(i).addr) & " Received: " & to_hstring(mem(reference(i).addr)) & " Expected: " & to_hstring(reference(i).data));
|
|
end loop;
|
|
end loop;
|
|
-- Toggle High for one clock cycle
|
|
mem_check_done <= '1';
|
|
wait until rising_edge(clk);
|
|
end process;
|
|
|
|
watchdog : process
|
|
begin
|
|
wait for 1 ms;
|
|
Alert("Test timeout", FAILURE);
|
|
std.env.stop;
|
|
end process;
|
|
|
|
end architecture; |