rtps-fpga/sim/L0_mem_ctrl_test1.do
Greek 52bd4053d1 Add mem_ctrl Level 0 Test 1
mem_ctrl fixed and testbench implemented
2021-02-17 14:01:49 +01:00

52 lines
2.5 KiB
Plaintext

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l0_mem_ctrl_test1/uut/clk
add wave -noupdate /l0_mem_ctrl_test1/uut/reset
add wave -noupdate -divider INPUT
add wave -noupdate /l0_mem_ctrl_test1/uut/ready_in
add wave -noupdate /l0_mem_ctrl_test1/uut/valid_in
add wave -noupdate -radix unsigned /l0_mem_ctrl_test1/uut/addr
add wave -noupdate -radix hexadecimal /l0_mem_ctrl_test1/uut/data_in
add wave -noupdate /l0_mem_ctrl_test1/uut/read
add wave -noupdate -divider MEMORY
add wave -noupdate -expand -group MEMORY -radix unsigned /l0_mem_ctrl_test1/uut/ram_inst/addr
add wave -noupdate -expand -group MEMORY -radix hexadecimal /l0_mem_ctrl_test1/uut/ram_inst/rd_data
add wave -noupdate -expand -group MEMORY /l0_mem_ctrl_test1/uut/ram_inst/ren
add wave -noupdate -expand -group MEMORY /l0_mem_ctrl_test1/uut/ram_inst/wen
add wave -noupdate -expand -group MEMORY -radix hexadecimal /l0_mem_ctrl_test1/uut/ram_inst/wr_data
add wave -noupdate -divider OUTPUT
add wave -noupdate /l0_mem_ctrl_test1/uut/ready_out
add wave -noupdate -radix hexadecimal /l0_mem_ctrl_test1/uut/data_out
add wave -noupdate /l0_mem_ctrl_test1/uut/valid_out
add wave -noupdate -divider MISC
add wave -noupdate /l0_mem_ctrl_test1/uut/delay_line
add wave -noupdate -radix unsigned /l0_mem_ctrl_test1/uut/delay_cnt
add wave -noupdate /l0_mem_ctrl_test1/uut/burst_fifo_inst/free
add wave -noupdate -divider FIFO
add wave -noupdate -group FIFO -radix hexadecimal /l0_mem_ctrl_test1/uut/burst_fifo_inst/data_in
add wave -noupdate -group FIFO /l0_mem_ctrl_test1/uut/burst_fifo_inst/read
add wave -noupdate -group FIFO /l0_mem_ctrl_test1/uut/burst_fifo_inst/write
add wave -noupdate -group FIFO -radix hexadecimal /l0_mem_ctrl_test1/uut/burst_fifo_inst/data_out
add wave -noupdate -group FIFO /l0_mem_ctrl_test1/uut/burst_fifo_inst/empty
add wave -noupdate -group FIFO /l0_mem_ctrl_test1/uut/burst_fifo_inst/free
add wave -noupdate -group FIFO /l0_mem_ctrl_test1/uut/burst_fifo_inst/full
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {574535 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 149
configure wave -valuecolwidth 144
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {1148342 ps}