- Handle case where packet end = submessage end (Avoid extra stage switches) - Fix last_word_out - Fix case where rd and empty are both high (INFO_TS) * Modify Endpoint Frame format of GAP - Add dummy word to avoid complexity * rtps_handler Testbench - Add check for last_word_out
326 lines
14 KiB
VHDL
326 lines
14 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm; -- Utility Library
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context osvvm.OsvvmContext;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.rtps_test_package.all;
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-- This testbench tests the Output Routing of the rtps_handler. It generates stimulus for different destinations and compares the selected output to the expected.
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-- This testbench covers following:
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-- * METATRAFFIC/USERTRAFFIC/UKNOWN Destination Addresses (All Address/Port Combinations)
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-- * UNKNOWN/BUILT-IN/USER/ENTITY_UNKNOWN Entity Destinations
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-- * READER/WRITER Source
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entity rtps_handler_test2 is
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end entity;
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architecture testbench of rtps_handler_test2 is
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-- *COMPONENT DECLARATION*
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component rtps_handler is
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port (
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clk : in std_logic; -- Input Clock
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reset : in std_logic; -- Synchronous Reset
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empty : in std_logic; -- Input FIFO empty flag
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rd : out std_logic; -- Input FIFO read signal
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data_in : in std_logic_vector(WORD_WIDTH-1 downto 0); -- Input FIFO data signal
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data_out : out std_logic_vector(WORD_WIDTH-1 downto 0); -- Output data signal
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builtin_full : in std_logic; -- Output FIFO (Built-In Endpoint) full signal
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builtin_wr : out std_logic; -- Output FIFO (Built-In Endpoint) write signal
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user_full : in std_logic_vector(0 to NUM_ENDPOINTS-1); -- Output FIFO (User Endpoints) full signal
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user_wr : out std_logic_vector(0 to NUM_ENDPOINTS-1); -- Output FIFO (User Endpoints) write signal
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last_word_out : out std_logic -- Output FIFO Last Word signal
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);
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end component;
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-- *TYPE DECLARATION*
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type TEST_STAGE_TYPE is (IDLE, BUSY);
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-- *SIGNAL DECLARATION*
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signal clk, reset, in_empty, rd_sig, builtin_full, builtin_wr, last_word_out : std_logic := '0';
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signal user_full, user_wr : std_logic_vector(0 to NUM_ENDPOINTS-1) := (others => '0');
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signal data_in, data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal stim_stage, ref_stage : TEST_STAGE_TYPE := IDLE;
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shared variable stimulus, dummy : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
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signal packet_sent, packet_checked : std_logic := '0';
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signal cnt_stim, cnt_ref : natural := 0;
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signal start : std_logic := '0';
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signal reference : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
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-- *FUNCTION DECLARATION*
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procedure wait_on_complete is
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begin
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wait until rising_edge(packet_sent);
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if (packet_checked /= '1') then
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wait until (packet_checked = '1');
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end if;
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end procedure;
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begin
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-- Unit Under Test
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uut : rtps_handler
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port map (
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clk => clk,
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reset => reset,
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empty => in_empty or packet_sent,
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rd => rd_sig,
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data_in => data_in,
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data_out => data_out,
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builtin_full => builtin_full,
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builtin_wr => builtin_wr,
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user_full => user_full,
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user_wr => user_wr,
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last_word_out => last_word_out
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);
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stimulus_prc : process
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variable rtps_header : RTPS_HEADER_TYPE := DEFAULT_RTPS_HEADER;
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variable rtps_data : RTPS_SUBMESSAGE_TYPE := DEFAULT_RTPS_SUBMESSAGE;
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variable check_cnt : natural := 0;
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variable RV : RandomPType;
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variable UDP : UDP_HEADER_TYPE;
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variable tmp_loc_list : LOCATOR_LIST_TYPE;
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variable ref1, ref2, ref3 : std_logic_vector(0 to NUM_ENDPOINTS);
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variable tmp_id : std_logic_vector(ENTITYID_WIDTH-1 downto 0);
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variable is_meta : boolean;
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-- Wrapper to use procedure as function
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impure function gen_rand_loc_2 return LOCATOR_TYPE is
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variable ret : LOCATOR_TYPE := EMPTY_LOCATOR;
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begin
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gen_rand_loc(RV, ret);
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return ret;
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end function;
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procedure start_test is
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begin
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start <= '1';
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wait until rising_edge(clk);
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start <= '0';
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wait until rising_edge(clk);
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end procedure;
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begin
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SetAlertLogName("L0-rtps_handler-output_routing");
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SetAlertEnable(FAILURE, TRUE);
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SetAlertEnable(ERROR, TRUE);
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SetAlertEnable(WARNING, TRUE);
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SetLogEnable(DEBUG, FALSE);
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SetLogEnable(PASSED, FALSE);
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SetLogEnable(INFO, TRUE);
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RV.InitSeed(RV'instance_name);
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-- UDP Header
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UDP := (src => gen_rand_loc_2, dest => EMPTY_LOCATOR);
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-- Default Valid Data Submessage
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rtps_data := DEFAULT_RTPS_SUBMESSAGE;
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rtps_data.flags(SUBMESSAGE_DATA_FLAG_POS) := '1';
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rtps_data.data := (length => 2, data => (0 => RV.RandSlv(WORD_WIDTH), 1 => RV.RandSlv(WORD_WIDTH), others => (others => '0')), last => (others => '0'));
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Log("Initiating Test", INFO);
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in_empty <= '0';
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builtin_full <= '0';
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user_full <= (others => '0');
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start <= '0';
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reset <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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reset <= '0';
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for i in 0 to 2 loop -- USER/META/UKNOWN Traffic
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case (i) is
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-- META TRAFFIC ADDRESSES
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when 0 =>
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tmp_loc_list := DEST_LOC.meta;
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ref1 := (NUM_ENDPOINTS => '1', others => '0');
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is_meta := TRUE;
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-- USER TRAFFIC ADDRESSES
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when 1 =>
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tmp_loc_list := DEST_LOC.user;
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ref1 := (NUM_ENDPOINTS => '0', others => '1');
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is_meta := FALSE;
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-- UKNOWN ADDRESSES
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when others =>
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ref1 := (others => '0');
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tmp_loc_list := ( numLocators => int(2,CDR_LONG_WIDTH),
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locator => (
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0 => (
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kind => LOCATOR_KIND_UDPv4,
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portn => (LOCATOR_PORT_WIDTH-1 downto UDP_PORT_WIDTH => '0') & META_IPv4_MULTICAST_PORT,
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addr => RV.RandSlv(LOCATOR_ADDR_WIDTH)
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),
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1 => (
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kind => LOCATOR_KIND_UDPv4,
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portn => RV.RandSlv(LOCATOR_PORT_WIDTH),
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addr => (LOCATOR_ADDR_WIDTH-1 downto IPv4_ADDRESS_WIDTH => '0') & DEFAULT_IPv4_META_ADDRESS
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),
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others => EMPTY_LOCATOR
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)
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);
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is_meta := FALSE;
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end case;
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for j in 0 to to_integer(unsigned(tmp_loc_list.numLocators))-1 loop -- Destination Address
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UDP.dest := tmp_loc_list.locator(j);
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for k in 0 to NUM_ENDPOINTS+2 loop -- Destination Entity ID
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case (k) is
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-- UKNOWN
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when NUM_ENDPOINTS =>
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ref2 := (others => '0');
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tmp_id := RV.RandSlv(ENTITYID_WIDTH);
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tmp_id(ENTITY_KIND_H_RANGE) := USER_DEFINED_ENTITY;
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tmp_id(ENTITY_KIND_L_RANGE) := UNKNOWN_KIND;
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-- ENTITYID_UKNOWN
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when NUM_ENDPOINTS+1 =>
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tmp_id := ENTITYID_UNKNOWN;
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ref2 := (others => '1');
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-- BUILT_IN
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when NUM_ENDPOINTS+2 =>
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tmp_id := ENTITYID_PARTICIPANT;
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ref2 := (NUM_ENDPOINTS => '1', others => '0');
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-- USER
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when others =>
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tmp_id := ENTITYID(k);
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ref2 := (k => '1', others => '0');
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end case;
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for l in 0 to 1 loop -- Reader/Writer Source
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case (l) is
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-- Writer Source
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when 0 =>
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rtps_data.submessageID := SID_DATA;
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rtps_data.readerId := tmp_id;
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rtps_data.writerId := DEFAULT_ENTITYID;
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ref3 := (NUM_ENDPOINTS => '1', NUM_READERS-1 downto 0 => '1', others => '0');
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-- Reader Source
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when others =>
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rtps_data.submessageID := SID_ACKNACK;
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rtps_data.readerId := DEFAULT_ENTITYID;
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rtps_data.writerId := tmp_id;
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ref3 := (NUM_ENDPOINTS => '1', NUM_ENDPOINTS-1 downto NUM_READERS => '1', others => '0');
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end case;
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-- *STIMULUS*
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Log("Sending Packet. Config i=" & integer'image(i) & ", j=" & integer'image(j) & ", k=" & integer'image(k) & ", l=" & integer'image(l), INFO);
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--report "ref1: " & to_string(ref1);
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--report "ref2: " & to_string(ref2);
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--report "ref3: " & to_string(ref3);
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-- UDP Header
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gen_udp_header(UDP, stimulus);
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-- RTPS Header
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gen_rtps_header(rtps_header, stimulus);
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-- Valid Data
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gen_rtps_submessage(rtps_data, stimulus);
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if ((ref1 and ref2 and ref3) /= (ref1'range => '0')) then
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gen_rtps_handler_out(rtps_data, UDP.src, is_meta, TIME_INVALID, rtps_header.guidPrefix, dummy);
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end if;
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-- Finalize Packet
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fix_udp_packet(stimulus);
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reference <= ref1 and ref2 and ref3;
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start_test;
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wait_on_complete;
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check_cnt := check_cnt + dummy.length;
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stimulus.length := 0;
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dummy.length := 0;
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end loop;
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end loop;
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end loop;
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end loop;
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AlertIf(GetAffirmCount < check_cnt, "Incomplete test run");
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ReportAlerts;
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std.env.stop;
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wait;
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end process;
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clock_prc : process
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begin
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clk <= '0';
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wait for 25 ns;
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clk <= '1';
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wait for 25 ns;
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end process;
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input_prc : process(all)
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begin
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data_in <= stimulus.data(cnt_stim);
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case (stim_stage) is
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when IDLE =>
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packet_sent <= '1';
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when BUSY =>
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packet_sent <= '0';
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end case;
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if rising_edge(clk) then
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if (reset = '1') then
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cnt_stim <= 0;
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stim_stage <= IDLE;
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else
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case (stim_stage) is
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when IDLE =>
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if (start = '1') then
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stim_stage <= BUSY;
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cnt_stim <= 0;
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end if;
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when BUSY =>
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if (cnt_stim = stimulus.length) then
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stim_stage <= IDLE;
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elsif (rd_sig = '1') then
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cnt_stim <= cnt_stim + 1;
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end if;
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end case;
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end if;
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end if;
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end process;
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output_prc : process(all)
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begin
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case (ref_stage) is
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when IDLE =>
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packet_checked <= '1';
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when BUSY =>
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packet_checked <= '0';
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end case;
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if rising_edge(clk) then
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if (reset = '1') then
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cnt_ref <= 0;
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ref_stage <= IDLE;
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else
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case (ref_stage) is
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when IDLE =>
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if (start = '1') then
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ref_stage <= BUSY;
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cnt_ref <= 0;
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end if;
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when BUSY =>
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if (cnt_ref = dummy.length) then
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ref_stage <= IDLE;
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elsif (builtin_wr = '1' or user_wr /= (0 to NUM_ENDPOINTS-1 => '0')) then
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AffirmIfEqual((user_wr & builtin_wr), reference);
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cnt_ref <= cnt_ref + 1;
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end if;
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end case;
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end if;
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end if;
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end process;
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watchdog : process
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begin
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wait for 1 ms;
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Alert("Test timeout", FAILURE);
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std.env.stop;
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end process;
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end architecture; |