10cda546bf
- IPv4 RFC - FPGA Network Stack Master Thesis * Updated .gitignore * Added Single Port RAM - Xillinx Specific * Added IPv4 Parser - Dynamic Re-assembly Buffer selection - Main entity documentation missing - Synthesized, but not tested or simulated * Added Vivado (Zedboard) project for synthesis testing
14 lines
184 B
Plaintext
14 lines
184 B
Plaintext
#Ignore List
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/syn/**
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/modelsim/**
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/download/**
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#Unignore Directories (Needed to unignore files in Subdirectories)
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!*/
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#WHITELIST
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#Vivado Project File
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!*.xpr
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#Modelsim Do files
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!*.do |