Greek 46ca2228b6 Add and Redefine existing Dual Port RAM Implementations ... Simple Dual Port (Read and Write Port), and True Dual Port RAM implementations, together with their respective Altera implementations were added. The 'arch' Architectures should have the same behaviour as the Altera Implementations (single_port_ram was modified to achieve that)		2021-12-09 19:44:40 +01:00
doc	Add documentation	2021-11-17 14:27:30 +01:00
sim	Add Test2 Level 2 testbench	2021-12-09 19:44:39 +01:00
src	Add and Redefine existing Dual Port RAM Implementations	2021-12-09 19:44:40 +01:00
syn	Add directive to allow QSYS Compilation	2021-12-09 19:44:38 +01:00
.gitattributes	* Added DDS/RTPS Documentation	2020-05-10 19:31:49 +02:00
.gitignore	code refactoring	2021-12-09 19:44:39 +01:00
.gitmodules	* Added OSVVM Library as Submodule	2020-11-15 20:34:39 +01:00
READ.txt	Add complete Level2 System Test	2021-11-17 14:23:53 +01:00
Report.txt	* Added Documentation	2020-05-24 13:08:03 +02:00
VHDL-2008.txt	Code Refactor	2021-05-15 20:39:56 +02:00