rtps-fpga/sim/L0_rtps_builtin_endpoint_test5.do
Greek 90a4c7928a Backport Memory Controller to rtps_builtin_endpoint
Backport Memory Controller and Memory FSM from RTPS/DDS Endpoints to
RTPS Builtin Endpoint.
The Memory is now using a single linked list and the FSM uses Frame Field
Flags.
The main FSM uses check_time to initiate stale checks, and the stale
checks are done in the main FSM.
Testbench was modified to accomodate the changes (Previous L0 Test4 was
removed and integrated in L0 Test 1).
2021-05-11 13:23:55 +02:00

79 lines
7.0 KiB
Plaintext

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/clk
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/reset
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/time
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/check_time
add wave -noupdate -divider INPUT
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/empty
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/rd
add wave -noupdate -radix hexadecimal /l0_rtps_builtin_endpoint_test5/uut/data_in
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/last_word_in
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/last_word_in_latch
add wave -noupdate -divider {MAIN FSM}
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/stage
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/stage_next
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/cnt
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/endpoint_mask
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/participant_match
add wave -noupdate -divider {MEM FSM}
add wave -noupdate -group MEMORY -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/addr
add wave -noupdate -group MEMORY /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/read
add wave -noupdate -group MEMORY /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/ready_in
add wave -noupdate -group MEMORY /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/valid_in
add wave -noupdate -group MEMORY -radix hexadecimal /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/data_in
add wave -noupdate -group MEMORY /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/ready_out
add wave -noupdate -group MEMORY /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/valid_out
add wave -noupdate -group MEMORY -radix hexadecimal /l0_rtps_builtin_endpoint_test5/uut/mem_ctrl_inst/data_out
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/mem_op_start
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/mem_opcode
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/mem_op_done
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/mem_stage
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/mem_stage_next
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/mem_cnt
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/mem_addr_base
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/mem_empty_head
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/mem_occupied_head
add wave -noupdate -childformat {{/l0_rtps_builtin_endpoint_test5/uut/participant_data.guid_prefix -radix hexadecimal} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.meta_addr -radix hexadecimal} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.def_addr -radix hexadecimal} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.meta_port -radix hexadecimal} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.def_port -radix hexadecimal} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.lease_duration -radix unsigned} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.lease_deadline -radix unsigned} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.heartbeat_res_time -radix unsigned} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.acknack_res_time -radix unsigned} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.spdp_seq_nr -radix unsigned} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.pub_seq_nr -radix unsigned} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.sub_seq_nr -radix unsigned} {/l0_rtps_builtin_endpoint_test5/uut/participant_data.mes_seq_nr -radix unsigned}} -subitemconfig {/l0_rtps_builtin_endpoint_test5/uut/participant_data.guid_prefix {-height 15 -radix hexadecimal} /l0_rtps_builtin_endpoint_test5/uut/participant_data.meta_addr {-height 15 -radix hexadecimal} /l0_rtps_builtin_endpoint_test5/uut/participant_data.def_addr {-height 15 -radix hexadecimal} /l0_rtps_builtin_endpoint_test5/uut/participant_data.meta_port {-height 15 -radix hexadecimal} /l0_rtps_builtin_endpoint_test5/uut/participant_data.def_port {-height 15 -radix hexadecimal} /l0_rtps_builtin_endpoint_test5/uut/participant_data.lease_duration {-height 15 -radix unsigned} /l0_rtps_builtin_endpoint_test5/uut/participant_data.lease_deadline {-height 15 -radix unsigned} /l0_rtps_builtin_endpoint_test5/uut/participant_data.heartbeat_res_time {-height 15 -radix unsigned} /l0_rtps_builtin_endpoint_test5/uut/participant_data.acknack_res_time {-height 15 -radix unsigned} /l0_rtps_builtin_endpoint_test5/uut/participant_data.spdp_seq_nr {-height 15 -radix unsigned} /l0_rtps_builtin_endpoint_test5/uut/participant_data.pub_seq_nr {-height 15 -radix unsigned} /l0_rtps_builtin_endpoint_test5/uut/participant_data.sub_seq_nr {-height 15 -radix unsigned} /l0_rtps_builtin_endpoint_test5/uut/participant_data.mes_seq_nr {-height 15 -radix unsigned}} /l0_rtps_builtin_endpoint_test5/uut/participant_data
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/current_pmf
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/mem_field_flags
add wave -noupdate -divider GUARD
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/read_cnt
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/parameter_end
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/parse_prc/rd_guard
add wave -noupdate -divider MISC
add wave -noupdate -radix unsigned /l0_rtps_builtin_endpoint_test5/uut/seq_nr
add wave -noupdate -divider TESTBENCH
add wave -noupdate -expand -group TESTBENCH /l0_rtps_builtin_endpoint_test5/start
add wave -noupdate -expand -group TESTBENCH /l0_rtps_builtin_endpoint_test5/stim_stage
add wave -noupdate -expand -group TESTBENCH /l0_rtps_builtin_endpoint_test5/stimulus.length
add wave -noupdate -expand -group TESTBENCH /l0_rtps_builtin_endpoint_test5/cnt_stim
add wave -noupdate -expand -group TESTBENCH /l0_rtps_builtin_endpoint_test5/packet_sent
add wave -noupdate -expand -group TESTBENCH /l0_rtps_builtin_endpoint_test5/check_done
add wave -noupdate -divider OUTPUT
add wave -noupdate -radix hexadecimal /l0_rtps_builtin_endpoint_test5/uut/data_out
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/endpoint_full
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/endpoint_wr
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/rtps_wr
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/rtps_full
add wave -noupdate /l0_rtps_builtin_endpoint_test5/uut/last_word_out
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {64726 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 149
configure wave -valuecolwidth 144
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {1148342 ps}