542 lines
24 KiB
VHDL
542 lines
24 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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architecture TYPENAME of key_holder is
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--*****COMPONENT DECLARATION*****
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component key_hash_generator is
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port (
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clk : in std_logic;
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reset : in std_logic;
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start : in std_logic;
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ack : out std_logic;
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data_in : in std_logic_vector(7 downto 0);
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valid_in : in std_logic;
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ready_in : out std_logic;
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last_word_in : in std_logic;
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key_hash : out std_logic_vector(127 downto 0);
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done : out std_logic
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);
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end component;
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--*****TYPE DECLARATION*****
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-- FSM states. Explained below in detail
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type STAGE_TYPE is (IDLE,START_KEY_HASH_GENERATION,GET_PAYLOAD_HEADER,FETCH,ALIGN_IN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD, WRITE_PAYLOAD_HEADER, PUSH,ALIGN_OUT_STREAM,ENCODE_PAYLOAD,GET_KEY_HASH,PUSH_KEY_HASH);
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-- ###GENERATED START###
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type DECODE_STAGE_TYPE is (GET_OPTIONAL_HEADER, TODO);
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type ENCODE_STAGE_TYPE is (TODO);
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-- TYPES DECLARATIONS
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-- ###GENERATED END###
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-- *MAIN PROCESS*
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signal stage, stage_next : STAGE_TYPE;
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signal cnt, cnt_next : natural range 0 to 5;
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signal endian_flag, endian_flag_next : std_logic;
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signal last_word_in_latch, last_word_in_latch_next : std_logic;
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signal decode_error_latch, decode_error_latch_next : std_logic;
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signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0);
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signal target_align, target_align_next : ALIGN_TYPE;
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signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal optional, optional_next : std_logic;
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signal abort_mem : std_logic;
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signal opcode_latch, opcode_latch_next : KEY_HOLDER_OPCODE_TYPE;
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signal cnt_2, cnt_2_next : natural range 0 to (WORD_WIDTH/BYTE_WIDTH)-1;
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signal align_op, align_op_next : std_logic;
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signal finalize_payload, finalize_payload_next : std_logic;
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signal ready_in_sig : std_logic;
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signal start_kh, ack_kh, done_kh : std_logic;
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signal data_in_kh : std_logic_vector(BYTE_WIDTH-1 downto 0);
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signal valid_in_kh, ready_in_kh, last_word_in_kh : std_logic;
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signal key_hash_kh : std_logic_vector(KEY_HASH_WIDTH-1 downto 0);
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signal key_hash, key_hash_next : KEY_HASH_TYPE;
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signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE;
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signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE;
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signal return_stage, return_stage_next : DECODE_STAGE_TYPE;
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-- ###GENERATED START###
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-- SIGNAL DECLARATION
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-- ###GENERATED END###
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--*****ALIAS DECLARATION*****
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alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
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alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
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alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_latch(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
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alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_latch(PARAMETER_LENGTH_WIDTH-1 downto 0);
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begin
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key_hash_generator_inst : key_hash_generator
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port map (
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clk => clk,
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reset => reset,
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start => start_kh,
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ack => ack_kh,
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data_in => data_in_kh,
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valid_in => valid_in_kh,
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ready_in => ready_in_kh,
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last_word_in => last_word_in_kh,
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key_hash => key_hash_kh,
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done => done_kh
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);
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-- ###GENERATED START###
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-- MEMORY INSTANTIATIONS
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-- ###GENERATED END###
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decode_error <= decode_error_latch;
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ready_in <= ready_in_sig;
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main_prc : process (all)
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variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
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variable cnt2_ref : std_logic_vector(1 downto 0);
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begin
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-- DEFAULT
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stage_next <= stage;
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decode_stage_next <= decode_stage;
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encode_stage_next <= encode_stage;
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return_stage_next <= return_stage;
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cnt_next <= cnt;
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cnt_2_next <= cnt_2;
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endian_flag_next <= endian_flag;
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last_word_in_latch_next <= last_word_in_latch;
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decode_error_latch_next <= decode_error_latch;
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align_offset_next <= align_offset;
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target_align_next <= target_align;
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optional_next <= optional;
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data_in_latch_next <= data_in_latch;
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data_out_latch_next <= data_out_latch;
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opcode_latch_next <= opcode_latch;
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key_hash_next <= key_hash;
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align_op_next <= align_op;
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finalize_payload_next <= finalize_payload;
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abort_mem <= '0';
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ack <= '0';
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ready_in_sig <= '0';
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last_word_out <= '0';
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valid_out <= '0';
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start_kh <= '0';
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valid_in_kh <= '0';
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last_word_in_kh <= '0';
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data_in_kh <= (others => '0');
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data_out <= (others => '0');
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-- ###GENERATED START###
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-- DEFAULT SIGNAL ASSIGNMENTS
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-- ###GENERATED END###
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-- Last Word Latch Setter
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if (last_word_in = '1') then
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last_word_in_latch_next <= '1';
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end if;
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case (stage) is
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when IDLE =>
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-- Latch Opcode
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opcode_latch_next <= opcode;
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if (start = '1') then
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case (opcode) is
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when PUSH_DATA =>
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ack <= '1';
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stage_next <= GET_PAYLOAD_HEADER;
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-- Reset
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key_hash_next <= KEY_HASH_NIL;
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when PUSH_SERIALIZED_KEY =>
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ack <= '1';
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stage_next <= GET_PAYLOAD_HEADER;
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-- Reset
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key_hash_next <= KEY_HASH_NIL;
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when READ_KEY_HASH =>
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ack <= '1';
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-- Key Hash not calculated
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if (key_hash = KEY_HASH_NIL) then
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stage_next <= START_KEY_HASH_GENERATION;
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else
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stage_next <= PUSH_KEY_HASH;
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cnt_next <= 0;
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end if;
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when READ_SERIALIZED_KEY =>
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ack <= '1';
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endian_flag_next <= LITTLE_ENDIAN;
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stage_next <= WRITE_PAYLOAD_HEADER;
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when others =>
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null;
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end case;
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end if;
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when START_KEY_HASH_GENERATION =>
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start_kh <= '1';
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-- <TYPENAME>KeyHolder is in PLAIN_CDR2 Big Endian encoding (see 7.6.8 DDS_XTYPES v1.3)
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endian_flag_next <= '0';
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-- Alignment Reset
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align_offset_next <= (others => '0');
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data_out_latch_next <= (others => '0');
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if (ack_kh = '1') then
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stage_next <= ENCODE_PAYLOAD;
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-- ###GENERATED START###
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encode_stage_next <= TODO;
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-- ###GENERATED START###
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end if;
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when GET_PAYLOAD_HEADER =>
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-- TODO: Latch Offset from Options Field?
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ready_in_sig <= '1';
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-- Input Guard
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if (valid_in = '1') then
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case (representation_id) is
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when CDR_BE =>
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endian_flag_next <= '0';
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stage_next <= FETCH;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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if (opcode_latch = PUSH_DATA) then
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-- ###GENERATED START###
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decode_stage_next <= TODO;
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-- ###GENERATED END###
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else --(opcode_latch = PUSH_SERIALIZED_KEY)
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assert(opcode_latch = PUSH_SERIALIZED_KEY) severity FAILURE;
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-- ###GENERATED START###
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decode_stage_next <= TODO;
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-- ###GENERATED END###
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end if;
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when CDR_LE =>
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endian_flag_next <= '1';
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stage_next <= FETCH;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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if (opcode_latch = PUSH_DATA) then
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-- ###GENERATED START###
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decode_stage_next <= TODO;
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-- ###GENERATED END###
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else --(opcode_latch = PUSH_SERIALIZED_KEY)
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assert(opcode_latch = PUSH_SERIALIZED_KEY) severity FAILURE;
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-- ###GENERATED START###
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decode_stage_next <= TODO;
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-- ###GENERATED END###
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end if;
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when others =>
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-- Unknown Payload Encoding
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stage_next <= SKIP_PAYLOAD;
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decode_error_latch_next <= '1';
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end case;
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end if;
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when FETCH =>
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ready_in_sig <= '1';
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-- Input Guard
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if (valid_in = '1') then
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data_in_latch_next <= data_in;
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-- Alignment Operation in progress
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if (align_op = '1') then
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stage_next <= ALIGN_IN_STREAM;
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-- Reset
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align_op_next <= '0';
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else
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stage_next <= DECODE_PAYLOAD;
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end if;
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end if;
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when ALIGN_IN_STREAM =>
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-- Target Stream Alignment reached
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if (check_align(align_offset, target_align)) then
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-- DONE
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stage_next <= DECODE_PAYLOAD;
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else
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align_offset_next <= align_offset + 1;
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-- Need to fetch new Input Word
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if (align_offset(1 downto 0) = "11") then
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align_op_next <= '1';
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stage_next <= FETCH;
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end if;
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end if;
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when SKIP_PAYLOAD =>
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if (last_word_in_latch = '0') then
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-- Skip Read
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ready_in_sig <= '1';
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else
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stage_next <= IDLE;
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-- Reset
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last_word_in_latch_next <= '0';
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end if;
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when DECODE_PAYLOAD =>
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case (decode_stage) is
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-- ###GENERATED START###
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when TODO =>
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-- ###GENERATED END###
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when GET_OPTIONAL_HEADER =>
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-- ALIGN GUARD
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if (not check_align(align_offset, ALIGN_4)) then
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target_align_next <= ALIGN_4;
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stage_next <= ALIGN_IN_STREAM;
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else
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case (cnt) is
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-- Optional Member Header
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when 0 =>
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-- Extended Parameter Header
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if (endian_swap(endian_flag,parameter_id) = PID_EXTENDED) then
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cnt_next <= cnt + 1;
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stage_next <= FETCH;
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else
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stage_next <= FETCH;
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decode_stage_next <= return_stage;
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cnt_next <= 0;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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-- Optional omitted
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if(endian_swap(endian_flag,parameter_length) = (parameter_length'reverse_range => '0')) then
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optional_next <= '0';
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else
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optional_next <= '1';
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end if;
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end if;
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-- eMemberHeader
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when 1 =>
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-- Ignore Parameter ID
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cnt_next <= cnt + 1;
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stage_next <= FETCH;
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-- Llength
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when 2 =>
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stage_next <= FETCH;
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decode_stage_next <= return_stage;
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cnt_next <= 0;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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-- Optional omitted
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if(endian_swap(endian_flag, data_in) = (data_in'reverse_range => '0')) then
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optional_next <= '0';
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else
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optional_next <= '1';
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end if;
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when others =>
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null;
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end case;
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end if;
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when others =>
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null;
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end case;
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when WRITE_PAYLOAD_HEADER =>
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valid_out <= '1';
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if (LITTLE_ENDIAN = '0') then
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data_out <= CDR_BE & x"0000";
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else
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data_out <= CDR_LE & x"0000";
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end if;
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-- Output Guard
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if (ready_out = '1') then
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stage_next <= ENCODE_PAYLOAD;
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-- Reset
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align_offset_next <= (others => '0');
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data_out_latch_next <= (others => '0');
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-- ###GENERATED START###
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encode_stage_next <= TODO;
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-- ###GENERATED END###
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end if;
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when PUSH =>
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-- Push to Key Hash Generator
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if (opcode_latch = READ_KEY_HASH) then
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-- XXX: Assumes data_out_latch is 32 bits (TODO)
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cnt2_ref := std_logic_vector(unsigned(align_offset(1 downto 0)) - to_unsigned(1,2));
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-- Mark Last Word
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if (finalize_payload = '1' and cnt_2 = to_integer(unsigned(cnt2_ref))) then
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last_word_in_kh <= '1';
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end if;
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valid_in_kh <= '1';
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data_in_kh <= get_sub_vector(data_out_latch, cnt_2, BYTE_WIDTH, TRUE);
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-- Output Guard
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if (ready_in_kh = '1') then
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-- Last Byte
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if (cnt_2 = to_integer(unsigned(cnt2_ref))) then
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-- Reset
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cnt_2_next <= 0;
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-- Alignment Operation in process
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if (align_op = '1') then
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stage_next <= ALIGN_OUT_STREAM;
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-- Reset
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align_op_next <= '0';
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-- DONE
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elsif (finalize_payload = '1') then
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stage_next <= GET_KEY_HASH;
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-- Reset
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finalize_payload_next <= '0';
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else
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stage_next <= ENCODE_PAYLOAD;
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end if;
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else
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cnt_2_next <= cnt_2 + 1;
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end if;
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end if;
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else -- (opcode_latch = READ_SERIALIZED_KEY)
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assert(opcode_latch = READ_SERIALIZED_KEY) severity FAILURE;
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-- Mark Last Word
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if (finalize_payload = '1') then
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last_word_out <= '1';
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end if;
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valid_out <= '1';
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data_out <= data_out_latch;
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-- Output Guard
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if (ready_out = '1') then
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-- NOTE: Ensures all padding is zero.
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data_out_latch_next <= (others => '0');
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-- Alignment Operation in process
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if (align_op = '1') then
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stage_next <= ALIGN_OUT_STREAM;
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-- Reset
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align_op_next <= '0';
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-- DONE
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elsif (finalize_payload = '1') then
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finalize_payload_next <= '0';
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stage_next <= IDLE;
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else
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stage_next <= ENCODE_PAYLOAD;
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end if;
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end if;
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end if;
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when ALIGN_OUT_STREAM =>
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-- Target Stream Alignment reached
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if (check_align(align_offset, target_align)) then
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-- DONE
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stage_next <= ENCODE_PAYLOAD;
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else
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align_offset_next <= align_offset + 1;
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-- Need to push Word
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if (align_offset(1 downto 0) = "11") then
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align_op_next <= '1';
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stage_next <= PUSH;
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end if;
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end if;
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when ENCODE_PAYLOAD =>
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case (encode_stage) is
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-- ###GENERATED START###
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when TODO =>
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-- ###GENERATED END###
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end case;
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when GET_KEY_HASH =>
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if (done_kh = '1') then
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key_hash_next <= to_key_hash(key_hash_kh);
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stage_next <= PUSH_KEY_HASH;
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cnt_next <= 0;
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end if;
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when PUSH_KEY_HASH =>
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case (cnt) is
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-- Key Hash 1/4
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when 0 =>
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data_out <= key_hash(0);
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valid_out <= '1';
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-- Output Guard
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if (ready_out = '1') then
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cnt_next <= cnt + 1;
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end if;
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-- Key Hash 2/4
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when 1 =>
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data_out <= key_hash(1);
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valid_out <= '1';
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-- Output Guard
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if (ready_out = '1') then
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cnt_next <= cnt + 1;
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end if;
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-- Key Hash 3/4
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when 2 =>
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data_out <= key_hash(2);
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valid_out <= '1';
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-- Output Guard
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if (ready_out = '1') then
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cnt_next <= cnt + 1;
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end if;
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-- Key Hash 4/4
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when 3 =>
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data_out <= key_hash(3);
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valid_out <= '1';
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last_word_out <= '1';
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-- Output Guard
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if (ready_out = '1') then
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-- DONE
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stage_next <= IDLE;
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end if;
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when others =>
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null;
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end case;
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when others =>
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null;
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end case;
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-- ABORT
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if (abort = '1' and stage /= IDLE) then
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stage_next <= IDLE;
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-- Reset
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last_word_in_latch_next <= '0';
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align_op_next <= '0';
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finalize_payload_next <= '0';
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-- OVERREAD GUARD
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-- Attempted read on empty input
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elsif (last_word_in_latch = '1' and last_word_in = '0' and ready_in_sig = '1') then
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stage_next <= SKIP_PAYLOAD;
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decode_error_latch_next <= '1';
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end if;
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end process;
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|
sync_prc : process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if (reset = '1') then
|
|
stage <= IDLE;
|
|
decode_stage <= TODO;
|
|
encode_stage <= TODO;
|
|
return_stage <= TODO;
|
|
target_align <= ALIGN_1;
|
|
opcode_latch <= NOP;
|
|
cnt <= 0;
|
|
cnt_2 <= 0;
|
|
endian_flag <= '0';
|
|
last_word_in_latch <= '0';
|
|
decode_error_latch <= '0';
|
|
optional <= '0';
|
|
align_op <= '0';
|
|
finalize_payload <= '0';
|
|
align_offset <= (others => '0');
|
|
data_in_latch <= (others => '0');
|
|
data_out_latch <= (others => '0');
|
|
key_hash <= KEY_HASH_NIL;
|
|
-- ###GENERATED START###
|
|
-- RESET SYNC SIGNAL VALUE
|
|
-- ###GENERATED END###
|
|
else
|
|
stage <= stage_next;
|
|
decode_stage <= decode_stage_next;
|
|
encode_stage <= encode_stage_next;
|
|
return_stage <= return_stage_next;
|
|
target_align <= target_align_next;
|
|
opcode_latch <= opcode_latch_next;
|
|
cnt <= cnt_next;
|
|
cnt_2 <= cnt_2_next;
|
|
endian_flag <= endian_flag_next;
|
|
last_word_in_latch <= last_word_in_latch_next;
|
|
decode_error_latch <= decode_error_latch_next;
|
|
optional <= optional_next;
|
|
align_op <= align_op_next;
|
|
finalize_payload <= finalize_payload_next;
|
|
align_offset <= align_offset_next;
|
|
data_in_latch <= data_in_latch_next;
|
|
data_out_latch <= data_out_latch_next;
|
|
key_hash <= key_hash_next;
|
|
-- ###GENERATED START###
|
|
-- SYNC SIGNALS
|
|
-- ###GENERATED END###
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end architecture; |