222 lines
10 KiB
VHDL
222 lines
10 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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entity test_loopback is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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-- READER
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start_r : out std_logic;
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ack_r : in std_logic;
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opcode_r : out DDS_READER_OPCODE_TYPE;
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instance_state_r : out std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
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view_state_r : out std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
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sample_state_r : out std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
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instance_handle_r : out INSTANCE_HANDLE_TYPE;
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max_samples_r : out std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
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get_data_r : out std_logic;
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done_r : in std_logic;
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return_code_r : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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si_sample_state_r : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
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si_view_state_r : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
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si_instance_state_r : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
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si_source_timestamp_r : in TIME_TYPE;
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si_instance_handle_r : in INSTANCE_HANDLE_TYPE;
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si_publication_handle_r : in INSTANCE_HANDLE_TYPE;
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si_disposed_generation_count_r : in std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0);
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si_no_writers_generation_count_r : in std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0);
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si_sample_rank_r : in std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0);
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si_generation_rank_r : in std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0);
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si_absolute_generation_rank_r : in std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0);
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si_valid_data_r : in std_logic;
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si_valid_r : in std_logic;
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si_ack_r : out std_logic;
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eoc_r : in std_logic;
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status_r : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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decode_error_r : in std_logic;
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id_r : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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a_r : in std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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valid_r : in std_logic;
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-- WRITER
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start_w : out std_logic;
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ack_w : in std_logic;
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opcode_w : out DDS_WRITER_OPCODE_TYPE;
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instance_handle_out_w : out INSTANCE_HANDLE_TYPE;
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source_ts_w : out TIME_TYPE;
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max_wait_w : out DURATION_TYPE;
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done_w : in std_logic;
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return_code_w : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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instance_handle_in_w : in INSTANCE_HANDLE_TYPE;
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status_w : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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id_w : out std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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a_w : out std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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encode_done_w : in std_logic
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);
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end entity;
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architecture arch of test_loopback is
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--*****TYPE DECLARATION*****
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type STAGE_TYPE is (INITIALIZE, IDLE, READ, PROCESS_MESSAGE, WRITE);
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--*****SIGNAL DECLARATION*****
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signal stage, stage_next : STAGE_TYPE;
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signal cnt, cnt_next : natural range 0 to 3;
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signal inst, inst_next : INSTANCE_HANDLE_TYPE;
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signal long, long_next : std_logic_vector(CDR_LONG_WIDTH-1 downto 0);
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begin
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main_prc : process(all)
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begin
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-- DEFAULT
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stage_next <= stage;
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cnt_next <= cnt;
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inst_next <= inst;
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long_next <= long;
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-- DEFAULT Unregistered
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start_r <= '0';
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opcode_r <= NOP;
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instance_state_r <= ANY_INSTANCE_STATE;
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view_state_r <= ANY_VIEW_STATE;
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sample_state_r <= ANY_SAMPLE_STATE;
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instance_handle_r <= HANDLE_NIL;
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max_samples_r <= (others => '0');
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get_data_r <= '0';
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si_ack_r <= '0';
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start_w <= '0';
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opcode_w <= NOP;
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instance_handle_out_w <= HANDLE_NIL;
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source_ts_w <= TIME_INVALID;
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max_wait_w <= DURATION_ZERO;
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id_w <= (others => '0');
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a_w <= (others => '0');
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case (stage) is
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-- Get the Instance Handle for the target Topic Instance
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when INITIALIZE =>
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id_w <= std_logic_vector(to_unsigned(1, CDR_LONG_WIDTH));
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case (cnt) is
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when 0 =>
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start_w <= '1';
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opcode_w <= REGISTER_INSTANCE;
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if (ack_w = '1') then
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cnt_next <= cnt + 1;
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end if;
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when 1 =>
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if (done_w = '1') then
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inst_next <= instance_handle_in_w;
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stage_next <= IDLE;
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end if;
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when others =>
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null;
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end case;
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when IDLE =>
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-- Reader has Available Data
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if (check_mask(status_r,DATA_AVAILABLE_STATUS)) then
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stage_next <= READ;
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cnt_next <= 0;
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end if;
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when READ =>
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case (cnt) is
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when 0 =>
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start_r <= '1';
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opcode_r <= TAKE_NEXT_SAMPLE;
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if (ack_r = '1') then
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cnt_next <= cnt + 1;
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end if;
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when 1 =>
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if (done_r = '1') then
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case (return_code_r) is
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when RETCODE_OK =>
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cnt_next <= cnt + 1;
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when RETCODE_NO_DATA =>
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stage_next <= IDLE;
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when others =>
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assert FALSE report "Unexpected DDS Reader Return Code" severity FAILURE;
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end case;
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end if;
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when 2 =>
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if (si_valid_r = '1') then
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si_ack_r <= '1';
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-- Target Instance with Data
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if (si_instance_handle_r = inst and si_valid_data_r = '1') then
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cnt_next <= cnt + 1;
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get_data_r <= '1';
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else
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-- Read next Sample
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cnt_next <= 0;
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end if;
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end if;
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when 3 =>
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if (valid_r = '1') then
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assert (id_r = std_logic_vector(to_unsigned(1,CDR_LONG_WIDTH))) severity FAILURE;
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long_next <= a_r;
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stage_next <= PROCESS_MESSAGE;
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end if;
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when others =>
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null;
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end case;
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when PROCESS_MESSAGE =>
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-- Add 1k to Message
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long_next <= std_logic_vector(unsigned(long) + to_unsigned(1000, CDR_LONG_WIDTH));
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stage_next <= WRITE;
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cnt_next <= 0;
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when WRITE =>
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id_w <= std_logic_vector(to_unsigned(2, CDR_LONG_WIDTH));
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a_w <= long;
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case (cnt) is
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when 0 =>
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start_w <= '1';
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opcode_w <= WRITE;
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if (ack_w = '1') then
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cnt_next <= cnt + 1;
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end if;
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when 1 =>
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if (done_w = '1') then
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case (return_code_w) is
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when RETCODE_OK =>
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stage_next <= READ;
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cnt_next <= 0;
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when RETCODE_OUT_OF_RESOURCES =>
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-- Retry
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cnt_next <= 0;
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when others =>
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assert FALSE report "Unexpected DDS Writer Return Code" severity FAILURE;
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end case;
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end if;
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when others =>
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null;
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end case;
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end case;
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end process;
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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stage <= INITIALIZE;
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inst <= HANDLE_NIL;
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cnt <= 0;
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long <= (others => '0');
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else
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stage <= stage_next;
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inst <= inst_next;
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cnt <= cnt_next;
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long <= long_next;
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end if;
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end if;
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end process;
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end architecture;
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