337 lines
12 KiB
VHDL
337 lines
12 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library osvvm; -- Utility Library
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context osvvm.OsvvmContext;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.rtps_test_package.all;
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-- This testbench tests the general behavior of the rtps_out entity. Following 3 tests are done in sequence:
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-- TEST 1
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-- Add 2 random sized packets to random input port t1. After t1 is beginning being processed add 2 random sized packets to a random input port t2 that is after the t1 input port,
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-- and add 2 random sized packets to a random input port t3 that is before the t1 input port. The packets should come in order : t1p1, t2p1, t3p1, t1p2, t2p2, t3p2.
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-- TEST 2
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-- Add 4 packets with sizes 4-Bytes, 3-Bytes, 2-Bytes, and 1-Bytes respectively to the input port t1. Add a maximum size packet at input port t2, and a oversized (over maximum size)
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-- at input port t3. The expected order should be: t1p1, t2p1.
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-- Note that during the beginning of this test the UUT should be processing input port t3.
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-- TEST 3
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-- Add one random sized packet to each available input port. The expected order is: t1+1p1, t1+2p1,...,t1p1.
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-- Note that during the beginning of this test the UUT should be processing input port t1.
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entity L0_rtps_out_test1 is
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end entity;
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architecture testbench of L0_rtps_out_test1 is
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-- *CONSTANT DECLARATION*
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constant MAX_SIZE : natural := 20;
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-- *TYPE DECLARATION*
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type TEST_STAGE_TYPE is (IDLE, BUSY);
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type TEST_PACKET_ARRAY_TYPE is array (0 to NUM_ENDPOINTS) of TEST_PACKET_TYPE;
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type TEST_STAGE_ARRAY_TYPE is array (0 to NUM_ENDPOINTS) of TEST_STAGE_TYPE;
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type CNT_STIM_ARRAY_TYPE is array (0 to NUM_ENDPOINTS) of natural;
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-- *SIGNAL DECLARATION*
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signal clk, wr_sig, full : std_logic := '0';
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signal reset : std_logic := '1';
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signal data_out : std_logic_vector(WORD_WIDTH-1 downto 0) := (others => '0');
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signal data_in : RTPS_OUT_DATA_TYPE := (others => (others => '0'));
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signal last_word_in, rd_sig, empty : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
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signal stim_stage : TEST_STAGE_ARRAY_TYPE := (others => IDLE);
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shared variable stimulus : TEST_PACKET_ARRAY_TYPE := (others => EMPTY_TEST_PACKET);
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signal packet_sent : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
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signal cnt_stim : CNT_STIM_ARRAY_TYPE := (others => 0);
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signal start : std_logic := '0';
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shared variable SB : osvvm.ScoreBoardPkg_slv.ScoreBoardPType;
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signal stim_done, check_done : std_logic := '0';
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-- *FUNCTION DECLARATION*
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procedure push_reference(index : in natural; input : in TEST_PACKET_TYPE) is
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variable tmp : natural := 0;
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variable header_start : natural := 0;
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variable packet_start : natural := input.length;
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variable len : natural := 0;
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begin
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for i in 0 to input.length-1 loop
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if (tmp = index) then
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SB.Push(input.data(i));
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-- Mark End of Header/Start of Packet
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end if;
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if (i = header_start and tmp = index) then
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packet_start := header_start+3;
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end if;
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-- Calculate and Push Length
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if (i = packet_start-1) then
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-- Count until End of Current Packet
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loop
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len := len + 1;
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if (input.last(len-1+packet_start) = '1') then
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exit;
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end if;
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end loop;
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SB.Push(std_logic_vector(to_unsigned(len, WORD_WIDTH)));
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end if;
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if (input.last(i) = '1') then
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tmp := tmp + 1;
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header_start := i+1;
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end if;
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end loop;
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end procedure;
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begin
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empty <= packet_sent;
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-- Unit Under Test
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uut : entity work.rtps_out(arch)
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generic map (
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MAX_BUFFER_SIZE => MAX_SIZE-3
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)
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port map (
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clk => clk,
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reset => reset,
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data_in => data_in,
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last_word_in=> last_word_in,
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rd => rd_sig,
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empty => empty,
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data_out => data_out,
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wr => wr_sig,
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full => full
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);
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stimulus_prc : process
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variable RV : RandomPType;
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variable t1, t2, t3 : natural := 0;
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variable tmp : std_logic_vector(0 to NUM_ENDPOINTS) := (others => '0');
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variable tmp_packet : TEST_PACKET_TYPE := EMPTY_TEST_PACKET;
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procedure gen_rand_packet(size : in natural; output : inout TEST_PACKET_TYPE) is
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variable tmp : natural := 0;
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begin
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if (size = 0) then
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tmp := RV.RandInt(4, MAX_SIZE-1);
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else
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tmp := size;
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end if;
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Log("Packet Size: " & to_string(tmp), DEBUG);
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for i in 0 to tmp-1 loop
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output.data(output.length) := RV.RandSlv(WORD_WIDTH);
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Log("DATA: " & to_hstring(output.data(output.length)), DEBUG);
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output.length := output.length + 1;
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end loop;
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output.last(output.length-1) := '1';
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end procedure;
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procedure start_test is
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begin
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start <= '1';
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wait until rising_edge(clk);
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start <= '0';
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wait until rising_edge(clk);
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end procedure;
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begin
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assert (NUM_ENDPOINTS >= 2) report "Testbench needs at least 2 Endpoints" severity FAILURE;
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assert (MAX_SIZE > 4) report "MAX_SIZE has to be larger than 4" severity FAILURE;
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SetAlertLogName("rtps_out - Level 0 - Generic");
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SetAlertEnable(FAILURE, TRUE);
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SetAlertEnable(ERROR, TRUE);
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SetAlertEnable(WARNING, TRUE);
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SetLogEnable(DEBUG, FALSE);
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SetLogEnable(PASSED, FALSE);
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SetLogEnable(INFO, TRUE);
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RV.InitSeed(RV'instance_name);
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--
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Log("Initiating Test", INFO);
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stim_done <= '0';
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start <= '0';
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reset <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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reset <= '0';
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Log("Begin Test 1", INFO);
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t1 := RV.RandInt(1, NUM_ENDPOINTS-1);
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Log("T1: " & to_string(t1), DEBUG);
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t2 := RV.RandInt(t1+1, NUM_ENDPOINTS);
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Log("T2: " & to_string(t2), DEBUG);
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t3 := RV.RandInt(0, t1-1);
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Log("T3: " & to_string(t3), DEBUG);
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-- Generate 2 Packets
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gen_rand_packet(0, stimulus(t1));
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gen_rand_packet(0, stimulus(t1));
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-- Push T1 Packet 0
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push_reference(0, stimulus(t1));
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start_test;
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-- Wait for UUT do reach t1
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wait until rd_sig(t1) = '1';
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-- Generate 2 Packets for T2 and T3
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gen_rand_packet(0, stimulus(t2));
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gen_rand_packet(0, stimulus(t2));
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gen_rand_packet(0, stimulus(t3));
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gen_rand_packet(0, stimulus(t3));
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-- Push T2 Packet 0
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push_reference(0, stimulus(t2));
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-- Push T3 Packet 0
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push_reference(0, stimulus(t3));
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-- Push T1 Packet 1
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push_reference(1, stimulus(t1));
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-- Push T2 Packet 1
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push_reference(1, stimulus(t2));
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-- Push T3 Packet 1
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push_reference(1, stimulus(t3));
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start_test;
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-- Wait until begining of t3 sending
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tmp := (others => '1');
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tmp(t3) := '0';
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wait on rd_sig until packet_sent = tmp and rd_sig = not tmp;
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-- Reset Input
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tmp_packet := stimulus(t3);
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stimulus := (others => EMPTY_TEST_PACKET);
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stimulus(t3) := tmp_packet;
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Log("Begin Test 2", INFO);
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-- Min Valid Packet
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gen_rand_packet(4, stimulus(t1));
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push_reference(0, stimulus(t1));
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-- MAX Valid Packet
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gen_rand_packet(MAX_SIZE, stimulus(t2));
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push_reference(0, stimulus(t2));
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-- Invalid Packet (Over size)
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gen_rand_packet(MAX_SIZE+1, stimulus(t3));
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-- Invalid Packet [Packet too small]
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gen_rand_packet(3, stimulus(t1));
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gen_rand_packet(2, stimulus(t1));
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gen_rand_packet(1, stimulus(t1));
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start_test;
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-- Wait until all but t1 sent
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tmp := (others => '1');
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tmp(t1) := '0';
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wait on rd_sig until packet_sent = tmp and rd_sig = not tmp;
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-- reset Input
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tmp_packet := stimulus(t1);
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stimulus := (others => EMPTY_TEST_PACKET) ;
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stimulus(t1) := tmp_packet;
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Log("Begin Test 3", INFO);
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for i in 1 to NUM_ENDPOINTS+1 loop
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t3 := (t1+i) mod (NUM_ENDPOINTS+1);
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Log("Generate package for input port : " & to_string(t3), DEBUG);
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gen_rand_packet(0, stimulus(t3));
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if (t3 = t1) then
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-- t1 has 4 Packets in Queue
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push_reference(4, stimulus(t3));
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else
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push_reference(0, stimulus(t3));
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end if;
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end loop;
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start_test;
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-- Wait until all sent
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wait on packet_sent until packet_sent(t1) = '1';
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TranscriptOpen(RESULTS_FILE, APPEND_MODE);
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SetTranscriptMirror;
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stim_done <= '1';
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wait until check_done = '1';
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AlertIf(not SB.empty, "Incomplete test run");
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ReportAlerts;
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TranscriptClose;
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std.env.stop;
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wait;
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end process;
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clock_prc : process
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begin
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clk <= '0';
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wait for 25 ns;
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clk <= '1';
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wait for 25 ns;
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end process;
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endpoint_full_prc : process
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begin
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full <= '0';
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wait until wr_sig = '1';
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wait until rising_edge(clk);
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full <= '1';
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wait until rising_edge(clk);
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end process;
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alert_prc : process(all)
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begin
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if rising_edge(clk) then
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alertif((empty and rd_sig) /= (rd_sig'range => '0'), "Input FIFO read signal high while empty signal high", ERROR);
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alertif((full and wr_sig) = '1', "Output FIFO write signal high while full signal high", ERROR);
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end if;
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end process;
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input_prc_gen : for i in 0 to NUM_ENDPOINTS generate
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begin
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input_prc : process(all)
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begin
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data_in(i) <= stimulus(i).data(cnt_stim(i));
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last_word_in(i) <= stimulus(i).last(cnt_stim(i));
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if rising_edge(clk) then
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if (reset = '1') then
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cnt_stim(i) <= 0;
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stim_stage(i) <= IDLE;
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packet_sent(i) <= '1';
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else
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case (stim_stage(i)) is
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when IDLE =>
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if (start = '1' and stimulus(i).length /= 0) then
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stim_stage(i) <= BUSY;
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packet_sent(i) <= '0';
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end if;
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when BUSY =>
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if (rd_sig(i) = '1') then
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if (cnt_stim(i) = stimulus(i).length-1) then
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stim_stage(i) <= IDLE;
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packet_sent(i) <= '1';
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cnt_stim(i) <= 0;
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else
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cnt_stim(i) <= cnt_stim(i) + 1;
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end if;
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end if;
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end case;
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end if;
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end if;
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end process;
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end generate;
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output_check_prc : process(all)
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begin
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check_done <= '0';
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if rising_edge(clk) then
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if (wr_sig = '1') then
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SB.Check(data_out);
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end if;
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if (stim_done = '1' and SB.empty) then
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check_done <= '1';
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end if;
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end if;
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end process;
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watchdog : process
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begin
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wait for 5 ms;
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Alert("Test timeout", FAILURE);
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std.env.stop;
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end process;
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end architecture; |