394 lines
20 KiB
VHDL
394 lines
20 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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use work.Type2_package.all;
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entity Type2_reader_wrapper is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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-- FROM DDS READER
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start_dds : out std_logic;
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ack_dds : in std_logic;
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opcode_dds : out DDS_READER_OPCODE_TYPE;
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instance_state_dds : out std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
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view_state_dds : out std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
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sample_state_dds : out std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
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instance_handle_dds : out INSTANCE_HANDLE_TYPE;
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max_samples_dds : out std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
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get_data_dds : out std_logic;
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done_dds : in std_logic;
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return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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ready_in_dds : out std_logic;
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valid_in_dds : in std_logic;
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data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_in_dds : in std_logic;
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-- Sample Info
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si_sample_state_dds : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
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si_view_state_dds : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
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si_instance_state_dds : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
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si_source_timestamp_dds : in TIME_TYPE;
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si_instance_handle_dds : in INSTANCE_HANDLE_TYPE;
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si_publication_handle_dds : in PUBLICATION_HANDLE_TYPE;
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si_disposed_generation_count_dds : in std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0);
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si_no_writers_generation_count_dds : in std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0);
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si_sample_rank_dds : in std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0);
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si_generation_rank_dds : in std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0);
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si_absolute_generation_rank_dds : in std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0);
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si_valid_data_dds : in std_logic;
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si_valid_dds : in std_logic;
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si_ack_dds : out std_logic;
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eoc_dds : in std_logic;
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-- Communication Status
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status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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-- TO USER ENTITY
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start_user : in std_logic;
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ack_user : out std_logic;
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opcode_user : in DDS_READER_OPCODE_TYPE;
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instance_state_user : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
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view_state_user : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
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sample_state_user : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
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instance_handle_user : in INSTANCE_HANDLE_TYPE;
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max_samples_user : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
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get_data_user : in std_logic;
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done_user : out std_logic;
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return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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-- Sample Info
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si_sample_state_user : out std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
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si_view_state_user : out std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
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si_instance_state_user : out std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
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si_source_timestamp_user : out TIME_TYPE;
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si_instance_handle_user : out INSTANCE_HANDLE_TYPE;
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si_publication_handle_user : out PUBLICATION_HANDLE_TYPE;
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si_disposed_generation_count_user : out std_logic_vector(DISPOSED_GENERATION_COUNT_WIDTH-1 downto 0);
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si_no_writers_generation_count_user : out std_logic_vector(NO_WRITERS_GENERATION_COUNT_WIDTH-1 downto 0);
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si_sample_rank_user : out std_logic_vector(SAMPLE_RANK_WIDTH-1 downto 0);
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si_generation_rank_user : out std_logic_vector(GENERATION_RANK_WIDTH-1 downto 0);
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si_absolute_generation_rank_user : out std_logic_vector(ABSOLUTE_GENERATION_COUNT_WIDTH-1 downto 0);
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si_valid_data_user : out std_logic;
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si_valid_user : out std_logic;
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si_ack_user : in std_logic;
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eoc_user : out std_logic;
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-- Communication Status
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status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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decode_error : out std_logic;
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-- ###GENERATED START###
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-- TYPE SPECIFIC PORTS
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-- ###GENERATED END###
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valid : out std_logic
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);
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end entity;
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architecture arch of Type2_reader_wrapper is
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--*****TYPE DECLARATION*****
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-- FSM states. Explained below in detail
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type STAGE_TYPE is (IDLE,GET_PAYLOAD_HEADER,FETCH,ALIGN_STREAM,SKIP_PAYLOAD,DECODE_PAYLOAD);
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-- ###GENERATED START###
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type DECODE_STAGE_TYPE is (GET_OPTIONAL_HEADER);
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-- TYPES DECLARATIONS
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-- ###GENERATED END###
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-- *MAIN PROCESS*
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signal stage, stage_next : STAGE_TYPE;
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signal cnt, cnt_next : natural range 0 to 5;
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signal endian_flag, endian_flag_next : std_logic;
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signal last_word_in_latch, last_word_in_latch_next : std_logic;
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signal decode_error_latch, decode_error_latch_next : std_logic;
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signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0);
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signal align_op, align_op_next : std_logic;
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signal target_align, target_align_next : ALIGN_TYPE;
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signal data_in_latch, data_in_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal optional, optional_next : std_logic;
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signal abort_mem : std_logic;
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signal ready_in_dds_sig : std_logic;
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signal valid_latch, valid_latch_next : std_logic;
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signal decode_stage, decode_stage_next : DECODE_STAGE_TYPE;
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signal return_stage, return_stage_next : DECODE_STAGE_TYPE;
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-- ###GENERATED START###
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-- SIGNAL DECLARATIONS
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-- ###GENERATED END###
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--*****ALIAS DECLARATION*****
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alias representation_id : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(WORD_WIDTH-1 downto WORD_WIDTH-PAYLOAD_REPRESENTATION_ID_WIDTH);
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alias representation_options : std_logic_vector(PAYLOAD_REPRESENTATION_ID_WIDTH-1 downto 0) is data_in_dds(PAYLOAD_REPRESENTATION_OPTIONS_WIDTH-1 downto 0);
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alias parameter_id : std_logic_vector(PARAMETER_ID_WIDTH-1 downto 0) is data_in_latch(WORD_WIDTH-1 downto WORD_WIDTH-PARAMETER_ID_WIDTH);
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alias parameter_length : std_logic_vector(PARAMETER_LENGTH_WIDTH-1 downto 0) is data_in_latch(PARAMETER_LENGTH_WIDTH-1 downto 0);
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begin
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-- ###GENERATED START###
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-- MEMORY INSTANTIATIONS
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-- ###GENERATED END###
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-- PASSTHROUGH
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start_dds <= start_user;
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ack_user <= ack_dds;
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opcode_dds <= opcode_user;
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instance_state_dds <= instance_state_user;
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view_state_dds <= view_state_user;
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sample_state_dds <= sample_state_user;
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instance_handle_dds <= instance_handle_user;
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max_samples_dds <= max_samples_user;
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get_data_dds <= get_data_user;
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done_user <= done_dds;
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return_code_user <= return_code_dds;
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si_sample_state_user <= si_sample_state_dds;
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si_view_state_user <= si_view_state_dds;
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si_instance_state_user <= si_instance_state_dds;
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si_source_timestamp_user <= si_source_timestamp_dds;
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si_instance_handle_user <= si_instance_handle_dds;
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si_publication_handle_user <= si_publication_handle_dds;
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si_disposed_generation_count_user <= si_disposed_generation_count_dds;
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si_no_writers_generation_count_user <= si_no_writers_generation_count_dds;
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si_sample_rank_user <= si_sample_rank_dds;
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si_generation_rank_user <= si_generation_rank_dds;
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si_absolute_generation_rank_user <= si_absolute_generation_rank_dds;
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si_valid_data_user <= si_valid_data_dds;
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si_valid_user <= si_valid_dds;
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si_ack_dds <= si_ack_user;
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eoc_user <= eoc_dds;
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status_user <= status_dds;
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valid <= valid_latch;
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decode_error <= decode_error_latch;
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ready_in_dds <= ready_in_dds_sig;
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-- ###GENERATED START###
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-- PORT SIGNAL CONNECTIONS
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-- ###GENERATED END###
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main_prc : process (all)
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variable tmp_length : unsigned(WORD_WIDTH-1 downto 0);
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begin
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-- DEFAULT
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stage_next <= stage;
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decode_stage_next <= decode_stage;
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return_stage_next <= return_stage;
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cnt_next <= cnt;
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endian_flag_next <= endian_flag;
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last_word_in_latch_next <= last_word_in_latch;
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decode_error_latch_next <= decode_error_latch;
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align_offset_next <= align_offset;
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target_align_next <= target_align;
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optional_next <= optional;
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valid_latch_next <= valid_latch;
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data_in_latch_next <= data_in_latch;
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align_op_next <= align_op;
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abort_mem <= '0';
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ready_in_dds_sig <= '0';
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-- ###GENERATED START###
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-- DEFAULT SIGNAL ASSIGNMENTS
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-- ###GENERATED END###
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-- Last Word Latch Setter
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if (last_word_in_dds = '1') then
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last_word_in_latch_next <= '1';
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end if;
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case (stage) is
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when IDLE =>
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-- User Requests Payload
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if (si_valid_dds = '1' and si_valid_data_dds = '1' and si_ack_user = '1' and get_data_user = '1') then
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stage_next <= GET_PAYLOAD_HEADER;
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-- RESET
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decode_error_latch_next <= '0';
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valid_latch_next <= '0';
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abort_mem <= '1';
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else
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-- ###GENERATED START###
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-- MEMORY SIGNAL CONNECTIONS
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-- ###GENERATED END###
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end if;
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when GET_PAYLOAD_HEADER =>
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-- TODO: Latch Offset from Options Field?
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ready_in_dds_sig <= '1';
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-- Input Guard
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if (valid_in_dds = '1') then
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case (representation_id) is
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when CDR_BE =>
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endian_flag_next <= '0';
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stage_next <= FETCH;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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-- ###GENERATED START###
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decode_stage_next <= TODO;
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-- ###GENERATED END###
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-- Initial Fetch
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when CDR_LE =>
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endian_flag_next <= '1';
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stage_next <= FETCH;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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-- ###GENERATED START###
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decode_stage_next <= TODO;
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-- ###GENERATED END###
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when others =>
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-- Unknown Payload Encoding
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stage_next <= SKIP_PAYLOAD;
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decode_error_latch_next <= '1';
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end case;
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end if;
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when FETCH =>
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ready_in_dds_sig <= '1';
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-- Input Guard
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if (valid_in_dds = '1') then
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data_in_latch_next <= data_in_dds;
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-- Alignment Operation in progress
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if (align_op = '1') then
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stage_next <= ALIGN_STREAM;
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-- Reset
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align_op_next <= '0';
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else
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stage_next <= DECODE_PAYLOAD;
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end if;
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end if;
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when ALIGN_STREAM =>
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-- Target Stream Alignment reached
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if (check_align(align_offset, target_align)) then
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-- DONE
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stage_next <= DECODE_PAYLOAD;
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else
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align_offset_next <= align_offset + 1;
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-- Need to fetch new Input Word
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if (align_offset(1 downto 0) = "11") then
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align_op_next <= '1';
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stage_next <= FETCH;
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end if;
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end if;
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when SKIP_PAYLOAD =>
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if (last_word_in_latch = '0' and last_word_in_dds = '0') then
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-- Skip Read
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ready_in_dds_sig <= '1';
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else
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stage_next <= IDLE;
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-- If no Decode Error, mark output as valid
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if (decode_error_latch = '0') then
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valid_latch_next <= '1';
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end if;
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-- Reset
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last_word_in_latch_next <= '0';
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end if;
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when DECODE_PAYLOAD =>
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case (decode_stage) is
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-- ###GENERATED START###
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when TODO =>
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-- ###GENERATED END###
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when GET_OPTIONAL_HEADER =>
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-- ALIGN GUARD
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if (not check_align(align_offset, ALIGN_4)) then
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target_align_next <= ALIGN_4;
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stage_next <= ALIGN_STREAM;
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else
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case (cnt) is
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-- Optional Member Header
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when 0 =>
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-- Extended Parameter Header
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if (endian_swap(endian_flag,parameter_id) = PID_EXTENDED) then
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cnt_next <= cnt + 1;
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stage_next <= FETCH;
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else
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stage_next <= FETCH;
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decode_stage_next <= return_stage;
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cnt_next <= 0;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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-- Optional omitted
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if(endian_swap(endian_flag,parameter_length) = (parameter_length'reverse_range => '0')) then
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optional_next <= '0';
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else
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optional_next <= '1';
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end if;
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end if;
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-- eMemberHeader
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when 1 =>
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-- Ignore Parameter ID
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cnt_next <= cnt + 1;
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stage_next <= FETCH;
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-- Llength
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when 2 =>
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stage_next <= FETCH;
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decode_stage_next <= return_stage;
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cnt_next <= 0;
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-- Alignment Reset
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align_offset_next <= (others => '0');
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-- Optional omitted
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if(endian_swap(endian_flag, data_in_dds) = (data_in_dds'reverse_range => '0')) then
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optional_next <= '0';
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else
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optional_next <= '1';
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end if;
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when others =>
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null;
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end case;
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end if;
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when others =>
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null;
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end case;
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when others =>
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null;
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end case;
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-- OVERREAD GUARD
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-- Attempted read on empty input
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if (last_word_in_latch = '1' and last_word_in_dds = '0' and ready_in_dds_sig = '1') then
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stage_next <= SKIP_PAYLOAD;
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decode_error_latch_next <= '1';
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end if;
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end process;
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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stage <= IDLE;
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decode_stage <= TODO;
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return_stage <= TODO;
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target_align <= ALIGN_1;
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cnt <= 0;
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endian_flag <= '0';
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last_word_in_latch <= '0';
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decode_error_latch <= '0';
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optional <= '0';
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valid_latch <= '0';
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align_op <= '0';
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align_offset <= (others => '0');
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data_in_latch <= (others => '0');
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-- ###GENERATED START###
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-- RESET SYNC SIGNAL VALUE
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-- ###GENERATED END###
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else
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stage <= stage_next;
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decode_stage <= decode_stage_next;
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return_stage <= return_stage_next;
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target_align <= target_align_next;
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cnt <= cnt_next;
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endian_flag <= endian_flag_next;
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last_word_in_latch <= last_word_in_latch_next;
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decode_error_latch <= decode_error_latch_next;
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optional <= optional_next;
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valid_latch <= valid_latch_next;
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align_op <= align_op_next;
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align_offset <= align_offset_next;
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data_in_latch <= data_in_latch_next;
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-- ###GENERATED START###
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-- SYNC SIGNALS
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-- ###GENERATED END###
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end if;
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end if;
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end process;
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end architecture; |