70ace14c6b
- UDP Protocol * Added Synthesis Report for IPv4 Parser with different buffer sizes * Small fixes in IPv4 Handler * Added addsub Entity * Added Checksum entity * Implemented RTPS Parser - Compiles in Modelsim * Backup Version of RTPS Parser to extract and implement UDP Checksuming * Updated RTPS Package * Added VHDL comilation test file
47 lines
1.2 KiB
VHDL
47 lines
1.2 KiB
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
|
|
entity addsub is
|
|
generic (
|
|
INPUT_WIDTH : integer := 32;
|
|
OUTPUT_WIDTH : integer := 16
|
|
);
|
|
port (
|
|
clk : in std_logic;
|
|
reset : in std_logic;
|
|
op : in std_logic_vector(1 downto 0);
|
|
input : in std_logic_vector(INPUT_WIDTH-1 downto 0);
|
|
output : out std_logic_vector(OUTPUT_WIDTH-1 downto 0);
|
|
done : out std_logic
|
|
);
|
|
end entity;
|
|
|
|
architecture arch of addsub is
|
|
|
|
--*****COMPONENT DECLARATION*****
|
|
entity addsub is
|
|
generic (
|
|
PIPELINE_STAGES : integer := 1;
|
|
DATA_WIDTH : integer := 32
|
|
);
|
|
port (
|
|
clk : in std_logic;
|
|
reset : in std_logic;
|
|
cin : in std_logic;
|
|
A : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
B : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
RES : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
|
cout : out std_logic
|
|
);
|
|
end entity;
|
|
|
|
--*****SIGNAl DECLARATION
|
|
signal result : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
|
|
signal carry : std_logic := '0';
|
|
|
|
begin
|
|
|
|
|
|
end architecture; |