b47d409f13
Remove non-Quartus-supported VHDL 2008 features. Remove inferred Latches. Add test Entities to see resulting hw synthesis of various code segments.
53 lines
1.2 KiB
VHDL
53 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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-- Test synthesis of 3-way min comparison
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entity test2 is
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port (
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clk : in std_logic;
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reset : in std_logic;
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t1 : in TIME_TYPE;
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t2 : in TIME_TYPE;
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t3 : in TIME_TYPE;
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t : in TIME_TYPE;
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t_out : out TIME_TYPE
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);
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end entity;
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architecture arch of test2 is
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function min_time(t1, t2, t3, t : TIME_TYPE) return TIME_TYPE is
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variable ret : TIME_TYPE;
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begin
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if (not (t1 <= t)) then
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ret := t1;
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end if;
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if (not (t2 <= t) and t2 < ret) then
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ret := t2;
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end if;
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if (not (t3 <= t) and t3 < ret) then
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ret := t3;
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end if;
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return ret;
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end function;
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begin
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process (all)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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t_out <= TIME_INVALID;
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else
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t_out <= min_time(t1,t2,t3,t);
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end if;
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end if;
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end process;
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end architecture;
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