113 lines
5.9 KiB
VHDL
113 lines
5.9 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.Type1_package.all;
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entity dds_reader_syn is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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time : in TIME_TYPE;
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-- FROM RTPS ENDPOINT
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start_rtps : in std_logic;
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opcode_rtps : in HISTORY_CACHE_OPCODE_TYPE;
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ack_rtps : out std_logic;
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done_rtps : out std_logic;
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ret_rtps : out HISTORY_CACHE_RESPONSE_TYPE;
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data_in_rtps : in std_logic_vector(WORD_WIDTH-1 downto 0);
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valid_in_rtps : in std_logic;
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ready_in_rtps : out std_logic;
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last_word_in_rtps : in std_logic;
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-- TO USER ENTITY
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start_dds : in std_logic;
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ack_dds : out std_logic;
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opcode_dds : in DDS_READER_OPCODE_TYPE;
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instance_state_dds : in std_logic_vector(INSTANCE_STATE_KIND_WIDTH-1 downto 0);
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view_state_dds : in std_logic_vector(VIEW_STATE_KIND_WIDTH-1 downto 0);
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sample_state_dds : in std_logic_vector(SAMPLE_STATE_KIND_WIDTH-1 downto 0);
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instance_handle_dds : in INSTANCE_HANDLE_TYPE;
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max_samples_dds : in std_logic_vector(MAX_SAMPLES_WIDTH-1 downto 0);
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get_data_dds : in std_logic;
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done_dds : out std_logic;
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return_code_dds : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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ready_out_dds : in std_logic;
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valid_out_dds : out std_logic;
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data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_out_dds : out std_logic;
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-- Sample Info
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sample_info : out SAMPLE_INFO_TYPE;
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sample_info_valid : out std_logic;
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sample_info_ack : in std_logic;
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eoc : out std_logic;
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-- Communication Status
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status : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of dds_reader_syn is
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begin
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if_gen : if (NUM_READERS > 0) generate
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syn_inst : entity work.dds_reader(arch)
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generic map (
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TIME_BASED_FILTER_QOS => ENDPOINT_CONFIG(0).TIME_BASED_FILTER_QOS,
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DEADLINE_QOS => ENDPOINT_CONFIG(0).DEADLINE_QOS,
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MAX_INSTANCES => ENDPOINT_CONFIG(0).MAX_INSTANCES,
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MAX_SAMPLES_PER_INSTANCE => ENDPOINT_CONFIG(0).MAX_SAMPLES_PER_INSTANCE,
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MAX_SAMPLES => ENDPOINT_CONFIG(0).MAX_SAMPLES,
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HISTORY_QOS => ENDPOINT_CONFIG(0).HISTORY_QOS,
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RELIABILITY_QOS => ENDPOINT_CONFIG(0).RELIABILITY_QOS,
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PRESENTATION_QOS => ENDPOINT_CONFIG(0).PRESENTATION_QOS,
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DESTINATION_ORDER_QOS => ENDPOINT_CONFIG(0).DESTINATION_ORDER_QOS,
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COHERENT_ACCESS => ENDPOINT_CONFIG(0).COHERENT_ACCESS,
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ORDERED_ACCESS => ENDPOINT_CONFIG(0).ORDERED_ACCESS,
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WITH_KEY => ENDPOINT_CONFIG(0).WITH_KEY,
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PAYLOAD_FRAME_SIZE => MAX_TYPE1_SIZE
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)
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port map (
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clk => clk,
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reset => reset,
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time => time,
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start_rtps => start_rtps,
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opcode_rtps => opcode_rtps,
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ack_rtps => ack_rtps,
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done_rtps => done_rtps,
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ret_rtps => ret_rtps,
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data_in_rtps => data_in_rtps,
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valid_in_rtps => valid_in_rtps,
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ready_in_rtps => ready_in_rtps,
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last_word_in_rtps => last_word_in_rtps,
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start_dds => start_dds,
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ack_dds => ack_dds,
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opcode_dds => opcode_dds,
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instance_state_dds => instance_state_dds,
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view_state_dds => view_state_dds,
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sample_state_dds => sample_state_dds,
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instance_handle_dds => instance_handle_dds,
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max_samples_dds => max_samples_dds,
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get_data_dds => get_data_dds,
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done_dds => done_dds,
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return_code_dds => return_code_dds,
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ready_out_dds => ready_out_dds,
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valid_out_dds => valid_out_dds,
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data_out_dds => data_out_dds,
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last_word_out_dds => last_word_out_dds,
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sample_info => sample_info,
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sample_info_valid => sample_info_valid,
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sample_info_ack => sample_info_ack,
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eoc => eoc,
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status => status
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);
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end generate;
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end architecture;
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