Greek64
5d9acb6f41
QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
50 lines
1.4 KiB
VHDL
50 lines
1.4 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity addsub is
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generic (
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INPUT_WIDTH : integer := 32;
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OUTPUT_WIDTH : integer := 16
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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op : in std_logic_vector(1 downto 0);
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input : in std_logic_vector(INPUT_WIDTH-1 downto 0);
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output : out std_logic_vector(OUTPUT_WIDTH-1 downto 0);
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done : out std_logic
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);
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end entity;
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architecture arch of addsub is
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--*****COMPONENT DECLARATION*****
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entity addsub is
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generic (
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PIPELINE_STAGES : integer := 1;
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DATA_WIDTH : integer := 32
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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cin : in std_logic;
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A : in std_logic_vector(DATA_WIDTH-1 downto 0);
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B : in std_logic_vector(DATA_WIDTH-1 downto 0);
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RES : out std_logic_vector(DATA_WIDTH-1 downto 0);
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cout : out std_logic
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);
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end entity;
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--*****SIGNAl DECLARATION
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signal result : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal carry : std_logic;
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begin
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end architecture;
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