Greek64
6724156e72
The sequential logic of the main FSM in dds_reader was just to big to pass the timing requirement of 50 MHz. All the DDS READ/TAKE relevant states were removed from the main FSM, and added to a seperate read FSM. This reduces the state numberes and state tarnsition logic of the main FSM, allowing it to pass the timing requirements.
145 lines
8.1 KiB
VHDL
145 lines
8.1 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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use work.Type1_package.all;
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entity dds_reader_syn is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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-- FROM RTPS ENDPOINT
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input : in std_logic_vector(13 downto 0);
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output : out std_logic_vector(24 downto 0)
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);
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end entity;
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architecture arch of dds_reader_syn is
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constant NUM_READERS : natural := 1;
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begin
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if_gen : if (NUM_READERS > 0) generate
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signal time : TIME_TYPE;
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signal start_rtps, ack_rtps, done_rtps, valid_in_rtps, ready_in_rtps, last_word_in_rtps, start_dds, ack_dds, get_data_dds, done_dds, valid_out_dds, ready_out_dds, last_word_out_dds, sample_info_valid, sample_info_ack, eoc : std_logic_vector(0 to NUM_READERS-1);
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signal opcode_rtps : HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal ret_rtps : HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal data_in_rtps, data_out_dds : WORD_ARRAY_TYPE(0 to NUM_READERS-1);
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signal opcode_dds : DDS_READER_OPCODE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal instance_state_dds : INSTANCE_STATE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal view_state_dds : VIEW_STATE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal sample_state_dds : SAMPLE_STATE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal instance_handle_dds : INSTANCE_HANDLE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal max_samples_dds : MAX_SAMPLES_ARRAY_TYPE(0 to NUM_READERS-1);
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signal return_code_dds : RETURN_CODE_ARRAY_TYPE(0 to NUM_READERS-1);
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signal sample_info : SAMPLE_INFO_ARRAY_TYPE(0 to NUM_READERS-1);
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signal status : STATUS_KIND_ARRAY_TYPE(0 to NUM_READERS-1);
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begin
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-- This process is here to reduce the port count (allowing the entity to be synthesized as top level), but still prevent the tool from optimizing any logic away.
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dummy_reducer : process (all)
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variable tmp : std_logic_vector(127 downto 0);
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begin
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if rising_edge(clk) then
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time <= to_double_word(to_unsigned(time)(62 downto 0) & input(0));
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for i in 0 to NUM_READERS-1 loop
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start_rtps(i) <= input(1);
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opcode_rtps(i) <= HISTORY_CACHE_OPCODE_TYPE'VAL(to_integer(unsigned(input)));
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data_in_rtps(i) <= data_in_rtps(i)(data_in_rtps(i)'length-2 downto 0) & input(2);
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valid_in_rtps(i) <= input(3);
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last_word_in_rtps(i) <= input(4);
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start_dds(i) <= input(5);
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opcode_dds(i) <= DDS_READER_OPCODE_TYPE'VAL(to_integer(unsigned(input)));
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instance_state_dds(i) <= instance_state_dds(i)(instance_state_dds(i)'length-2 downto 0) & input(6);
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view_state_dds(i) <= view_state_dds(i)(view_state_dds(i)'length-2 downto 0) & input(7);
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sample_state_dds(i) <= sample_state_dds(i)(sample_state_dds(i)'length-2 downto 0) & input(8);
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tmp := std_logic_vector(to_unsigned(instance_handle_dds(i))(126 downto 0) & input(9));
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instance_handle_dds(i) <= to_key_hash(tmp);
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max_samples_dds(i) <= max_samples_dds(i)(max_samples_dds(i)'length-2 downto 0) & input(10);
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get_data_dds(i) <= input(11);
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ready_out_dds(i) <= input(12);
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sample_info_ack(i) <= input(13);
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end loop;
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end if;
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for i in 0 to NUM_READERS-1 loop
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output(0) <= ack_rtps(i);
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output(1) <= done_rtps(i);
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output(2) <= to_unsigned(HISTORY_CACHE_RESPONSE_TYPE'POS(ret_rtps(i)),1)(0);
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output(3) <= ready_in_rtps(i);
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output(4) <= ack_dds(i);
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output(5) <= done_dds(i);
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output(6) <= return_code_dds(i)(to_integer(unsigned(input)));
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output(7) <= valid_out_dds(i);
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output(8) <= data_out_dds(i)(to_integer(unsigned(input)));
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output(9) <= last_word_out_dds(i);
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output(10) <= sample_info(i).sample_state(to_integer(unsigned(input)));
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output(11) <= sample_info(i).view_state(to_integer(unsigned(input)));
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output(12) <= sample_info(i).instance_state(to_integer(unsigned(input)));
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output(13) <= to_unsigned(sample_info(i).source_timestamp)(to_integer(unsigned(input)));
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output(14) <= to_unsigned(sample_info(i).instance_handle)(to_integer(unsigned(input)));
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output(15) <= to_unsigned(sample_info(i).publication_handle)(to_integer(unsigned(input)));
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output(16) <= sample_info(i).disposed_generation_count(to_integer(unsigned(input)));
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output(17) <= sample_info(i).no_writers_generation_count(to_integer(unsigned(input)));
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output(18) <= sample_info(i).sample_rank(to_integer(unsigned(input)));
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output(19) <= sample_info(i).generation_rank(to_integer(unsigned(input)));
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output(20) <= sample_info(i).absolute_generation_rank(to_integer(unsigned(input)));
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output(21) <= sample_info(i).valid_data;
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output(22) <= sample_info_valid(i);
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output(23) <= eoc(i);
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output(24) <= status(i)(to_integer(unsigned(input)));
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end loop;
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end process;
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syn_inst : entity work.dds_reader(arch)
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generic map (
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NUM_READERS => NUM_READERS,
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CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to NUM_READERS-1)),
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MAX_REMOTE_ENDPOINTS => 50
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)
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port map (
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clk => clk,
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reset => reset,
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time => time,
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start_rtps => start_rtps,
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opcode_rtps => opcode_rtps,
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ack_rtps => ack_rtps,
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done_rtps => done_rtps,
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ret_rtps => ret_rtps,
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data_in_rtps => data_in_rtps,
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valid_in_rtps => valid_in_rtps,
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ready_in_rtps => ready_in_rtps,
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last_word_in_rtps => last_word_in_rtps,
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start_dds => start_dds,
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ack_dds => ack_dds,
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opcode_dds => opcode_dds,
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instance_state_dds => instance_state_dds,
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view_state_dds => view_state_dds,
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sample_state_dds => sample_state_dds,
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instance_handle_dds => instance_handle_dds,
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max_samples_dds => max_samples_dds,
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get_data_dds => get_data_dds,
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done_dds => done_dds,
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return_code_dds => return_code_dds,
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ready_out_dds => ready_out_dds,
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valid_out_dds => valid_out_dds,
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data_out_dds => data_out_dds,
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last_word_out_dds => last_word_out_dds,
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sample_info => sample_info,
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sample_info_valid => sample_info_valid,
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sample_info_ack => sample_info_ack,
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eoc => eoc,
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status => status
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);
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end generate;
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end architecture;
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