QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
76 lines
2.3 KiB
VHDL
76 lines
2.3 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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package math_pkg is
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-- calculates the logarithm dualis of the operand and rounds up
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-- the result to the next integer value.
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function log2c(constant value : in integer) return integer;
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-- returns the maximum of the two operands
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function max(constant value1, value2 : in integer) return integer;
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-- returns the maximum of the three operands
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function max(constant value1, value2, value3 : in integer) return integer;
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-- returns the minimum of the two operands
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function min(constant value1, value2 : in integer) return integer;
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function round_div(constant divident, divisor : in integer) return integer;
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end package;
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package body math_pkg is
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--*****FUNCTION DEFINITION*****
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function log2c(constant value : in integer) return integer is
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variable ret_value : integer;
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variable cur_value : integer;
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begin
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ret_value := 0;
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cur_value := 1;
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while cur_value < value loop
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ret_value := ret_value + 1;
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cur_value := cur_value * 2;
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end loop;
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return ret_value;
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end function;
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function max(constant value1, value2 : in integer) return integer is
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variable ret_value : integer;
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begin
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if value1 > value2 then
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ret_value := value1;
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else
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ret_value := value2;
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end if;
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return ret_value;
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end function;
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function max(constant value1, value2, value3 : in integer) return integer is
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begin
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return max(max(value1, value2), value3);
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end function;
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function min(constant value1, value2 : in integer) return integer is
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variable ret_value : integer;
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begin
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if value1 < value2 then
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ret_value := value1;
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else
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ret_value := value2;
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end if;
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return ret_value;
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end function;
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-- TODO: Rename to ceil_div, since we do not actually round
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function round_div(constant divident, divisor : in integer) return integer is
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variable ret : integer;
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begin
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ret := divident / divisor;
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if (divident mod divisor /= 0) then
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ret := ret + 1;
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end if;
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return ret;
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end function;
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end package body;
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