John Daktylidis
35baf341c7
The ready/valid Signals were missing from the DDS Reader and Writer Interfaces, preventing the user from effectively using non-Type dependent operations (like GET_OFFERED_DEADLINE_MISSED_STATUS). The L1_Type1_test1 was extended to test for this non-type dependent operation.
268 lines
11 KiB
VHDL
268 lines
11 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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entity TYPENAME_writer_interface is
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generic (
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LITTLE_ENDIAN : std_logic := '0'
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);
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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-- FROM DDS WRITER
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start_dds : out std_logic;
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ack_dds : in std_logic;
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opcode_dds : out DDS_WRITER_OPCODE_TYPE;
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instance_handle_in_dds : out INSTANCE_HANDLE_TYPE;
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source_ts_dds : out TIME_TYPE;
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max_wait_dds : out DURATION_TYPE;
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done_dds : in std_logic;
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return_code_dds : in std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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instance_handle_out_dds : in INSTANCE_HANDLE_TYPE;
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valid_out_dds : out std_logic;
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ready_out_dds : in std_logic;
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data_out_dds : out std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_out_dds : out std_logic;
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valid_in_dds : in std_logic;
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ready_in_dds : out std_logic;
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data_in_dds : in std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_in_dds : in std_logic;
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-- Communication Status
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status_dds : in std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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-- TO USER ENTITY
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start_user : in std_logic;
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ack_user : out std_logic;
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opcode_user : in DDS_WRITER_OPCODE_TYPE;
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instance_handle_in_user : in INSTANCE_HANDLE_TYPE;
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source_ts_user : in TIME_TYPE;
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max_wait_user : in DURATION_TYPE;
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done_user : out std_logic;
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return_code_user : out std_logic_vector(RETURN_CODE_WIDTH-1 downto 0);
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instance_handle_out_user : out INSTANCE_HANDLE_TYPE;
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valid_out_user : out std_logic;
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ready_out_user : in std_logic;
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data_out_user : out std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_out_user : out std_logic;
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-- Communication Status
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status_user : out std_logic_vector(STATUS_KIND_WIDTH-1 downto 0);
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-- ###GENERATED START###
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-- TYPE SPECIFIC PORTS
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-- ###GENERATED END###
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encode_done : out std_logic
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);
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end entity;
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architecture arch of TYPENAME_writer_interface is
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--*****TYPE DECLARATION*****
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-- FSM states. Explained below in detail
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type STAGE_TYPE is (IDLE,WRITE_PAYLOAD_HEADER,PUSH,ALIGN_STREAM,ENCODE_PAYLOAD);
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-- ###GENERATED START###
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type ENCODE_STAGE_TYPE is (TODO);
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-- TYPES DECLARATIONS
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-- ###GENERATED END###
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-- *MAIN PROCESS*
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signal stage, stage_next : STAGE_TYPE;
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signal cnt, cnt_next : natural range 0 to 5;
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signal align_offset, align_offset_next : unsigned(MAX_ALIGN_OFFSET_WIDTH-1 downto 0);
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signal align_op, align_op_next : std_logic;
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signal target_align, target_align_next : ALIGN_TYPE;
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signal data_out_latch, data_out_latch_next : std_logic_vector(WORD_WIDTH-1 downto 0);
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signal abort_mem : std_logic;
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signal finalize_payload, finalize_payload_next : std_logic;
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signal encode_stage, encode_stage_next : ENCODE_STAGE_TYPE;
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-- ###GENERATED START###
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-- SIGNAL DECLARATION
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-- ###GENERATED END###
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begin
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-- ###GENERATED START###
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-- MEMORY INSTANTIATIONS
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-- ###GENERATED END###
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-- PASSTHROUGH
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start_dds <= start_user;
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ack_user <= ack_dds;
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opcode_dds <= opcode_user;
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instance_handle_in_dds <= instance_handle_in_user;
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source_ts_dds <= source_ts_user;
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max_wait_dds <= max_wait_user;
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done_user <= done_dds;
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return_code_user <= return_code_dds;
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instance_handle_out_user <= instance_handle_out_dds;
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status_user <= status_dds;
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valid_out_user <= valid_in_dds;
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ready_in_dds <= ready_out_user;
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data_out_user <= data_in_dds;
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last_word_out_user <= last_word_in_dds;
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-- ###GENERATED START###
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-- PORT SIGNAL CONNECTIONS
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-- ###GENERATED END###
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main_prc : process (all)
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begin
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-- DEFAULT
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stage_next <= stage;
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encode_stage_next <= encode_stage;
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cnt_next <= cnt;
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align_offset_next <= align_offset;
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align_op_next <= align_op;
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target_align_next <= target_align;
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data_out_latch_next <= data_out_latch;
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finalize_payload_next <= finalize_payload;
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abort_mem <= '0';
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encode_done <= '0';
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valid_out_dds <= '0';
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last_word_out_dds <= '0';
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data_out_dds <= (others => '0');
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-- ###GENERATED START###
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-- DEFAULT SIGNAL ASSIGNMENTS
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-- ###GENERATED END###
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case (stage) is
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when IDLE =>
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-- User Requests Payload
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if (start_user = '1' and ack_dds = '1') then
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case (opcode_user) is
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when REGISTER_INSTANCE =>
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stage_next <= WRITE_PAYLOAD_HEADER;
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-- RESET
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abort_mem <= '1';
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when UNREGISTER_INSTANCE =>
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stage_next <= WRITE_PAYLOAD_HEADER;
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-- RESET
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abort_mem <= '1';
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when LOOKUP_INSTANCE =>
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stage_next <= WRITE_PAYLOAD_HEADER;
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-- RESET
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abort_mem <= '1';
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when WRITE =>
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stage_next <= WRITE_PAYLOAD_HEADER;
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-- RESET
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abort_mem <= '1';
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when DISPOSE =>
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stage_next <= WRITE_PAYLOAD_HEADER;
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-- RESET
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abort_mem <= '1';
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when others =>
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null;
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end case;
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else
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-- ###GENERATED START###
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-- MEMORY SIGNAL CONNECTIONS
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-- ###GENERATED END###
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end if;
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when WRITE_PAYLOAD_HEADER =>
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valid_out_dds <= '1';
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if (LITTLE_ENDIAN = '0') then
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data_out_dds <= CDR_BE & x"0000";
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else
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data_out_dds <= CDR_LE & x"0000";
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end if;
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-- Output Guard
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if (ready_out_dds = '1') then
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stage_next <= ENCODE_PAYLOAD;
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-- Reset
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align_offset_next <= (others => '0');
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data_out_latch_next <= (others => '0');
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-- ###GENERATED START###
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encode_stage_next <= TODO;
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-- ###GENERATED END###
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end if;
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when PUSH =>
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-- Mark Last Word
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if (finalize_payload = '1') then
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last_word_out_dds <= '1';
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end if;
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valid_out_dds <= '1';
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data_out_dds <= data_out_latch;
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-- Output Guard
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if (ready_out_dds = '1') then
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-- NOTE: Ensures all padding is zero.
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data_out_latch_next <= (others => '0');
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-- Alignment Operation in process
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if (align_op = '1') then
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stage_next <= ALIGN_STREAM;
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-- Reset
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align_op_next <= '0';
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-- DONE
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elsif (finalize_payload = '1') then
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finalize_payload_next <= '0';
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stage_next <= IDLE;
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else
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stage_next <= ENCODE_PAYLOAD;
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end if;
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end if;
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when ALIGN_STREAM =>
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-- Target Stream Alignment reached
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if (check_align(align_offset, target_align)) then
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-- DONE
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stage_next <= ENCODE_PAYLOAD;
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else
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align_offset_next <= align_offset + 1;
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-- Need to push Word
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if (align_offset(1 downto 0) = "11") then
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align_op_next <= '1';
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stage_next <= PUSH;
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end if;
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end if;
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when ENCODE_PAYLOAD =>
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case (encode_stage) is
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-- ###GENERATED START###
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when TODO =>
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-- ###GENERATED END###
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when others =>
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null;
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end case;
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when others =>
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null;
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end case;
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end process;
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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stage <= IDLE;
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encode_stage <= TODO;
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target_align <= ALIGN_1;
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cnt <= 0;
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finalize_payload <= '0';
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align_op <= '0';
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align_offset <= (others => '0');
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data_out_latch <= (others => '0');
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-- ###GENERATED START###
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-- RESET SYNC SIGNAL VALUE
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-- ###GENERATED END###
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else
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stage <= stage_next;
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encode_stage <= encode_stage_next;
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target_align <= target_align_next;
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cnt <= cnt_next;
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finalize_payload <= finalize_payload_next;
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align_op <= align_op_next;
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align_offset <= align_offset_next;
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data_out_latch <= data_out_latch_next;
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-- ###GENERATED START###
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-- SYNC SIGNALS
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-- ###GENERATED END###
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end if;
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end if;
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end process;
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end architecture; |