John Daktylidis
4c51a3944a
The UDP loopback just reads from the input FIFO, reverses src and destination addresses, and writes back to the output FIFO. This can be used to measure the throughput of the HPS-FPGA communication
130 lines
4.5 KiB
Tcl
130 lines
4.5 KiB
Tcl
# TCL File Generated by Component Editor 21.1
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# Thu Jul 27 13:57:40 GMT+02:00 2023
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# DO NOT MODIFY
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#
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# test_fpga "test_fpga" v1.0
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# 2023.07.27.13:57:40
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# Test PL-PS Communication
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module test_fpga
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#
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set_module_property DESCRIPTION "Test PL-PS Communication"
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set_module_property NAME test_fpga
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME test_fpga
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_top
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file test_top.vhd VHDL PATH ../test_top.vhd TOP_LEVEL_FILE
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add_fileset_file FWFT_FIFO.vhd VHDL PATH ../../src/FWFT_FIFO.vhd
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add_fileset_file FWFT_FIFO_Altera.vhd VHDL PATH ../../src/FWFT_FIFO_Altera.vhd
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add_fileset_file FWFT_FIFO_cfg.vhd VHDL PATH ../../src/FWFT_FIFO_cfg.vhd
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add_fileset_file Avalon_MM_wrapper.vhd VHDL PATH ../../src/Avalon_MM_wrapper.vhd
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add_fileset_file loopback.vhd VHDL PATH ../loopback.vhd
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add_fileset_file math_pkg.vhd VHDL PATH ../../src/math_pkg.vhd
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add_fileset_file rtps_config_package.vhd VHDL PATH ../../src/rtps_config_package.vhd
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add_fileset_file rtps_package.vhd VHDL PATH ../../src/rtps_package.vhd
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add_fileset_file TEMPLATE_user_config.vhd VHDL PATH ../../src/TEMPLATE_user_config.vhd
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset reset Input 1
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#
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# connection point avalon_slave_0
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#
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add_interface avalon_slave_0 avalon end
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set_interface_property avalon_slave_0 addressUnits WORDS
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set_interface_property avalon_slave_0 associatedClock clock
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set_interface_property avalon_slave_0 associatedReset reset
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set_interface_property avalon_slave_0 bitsPerSymbol 8
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set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave_0 burstcountUnits WORDS
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set_interface_property avalon_slave_0 explicitAddressSpan 0
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set_interface_property avalon_slave_0 holdTime 0
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set_interface_property avalon_slave_0 linewrapBursts false
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set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
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set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
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set_interface_property avalon_slave_0 readLatency 0
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set_interface_property avalon_slave_0 readWaitTime 1
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set_interface_property avalon_slave_0 setupTime 0
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set_interface_property avalon_slave_0 timingUnits Cycles
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set_interface_property avalon_slave_0 writeWaitTime 0
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set_interface_property avalon_slave_0 ENABLED true
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set_interface_property avalon_slave_0 EXPORT_OF ""
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set_interface_property avalon_slave_0 PORT_NAME_MAP ""
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set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave_0 address address Input 2
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add_interface_port avalon_slave_0 read read Input 1
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add_interface_port avalon_slave_0 write write Input 1
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add_interface_port avalon_slave_0 readdata readdata Output 32
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add_interface_port avalon_slave_0 writedata writedata Input 32
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add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
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