57 lines
1.5 KiB
VHDL
57 lines
1.5 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.test_package.all;
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-- Test synthesis of array indexing
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entity test7 is
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port (
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clk : in std_logic;
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reset : in std_logic;
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in1 : in std_logic;
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in2 : in std_logic;
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output : out std_logic_vector(84 downto 0)
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);
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end entity;
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architecture arch of test7 is
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signal a : std_logic_vector(52 downto 0);
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signal b : std_logic_vector(31 downto 0);
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signal res : std_logic_vector(84 downto 0);
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begin
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output <= res;
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mult_inst : entity work.mult(SYN)
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generic map (
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PIPELINE_STAGES => 1,
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DATAA_WIDTH => 32,
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DATAB_WIDTH => 53,
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DATAB_CONST => FALSE
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)
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port map (
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clk => clk,
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reset => reset,
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dataa => a,
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datab => b,
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result => res
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);
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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a <= (others => '0');
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b <= (others => '0');
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else
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a <= a(51 downto 0) & in1;
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b <= b(30 downto 0) & in2;
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end if;
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end if;
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end process;
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end architecture; |