52 lines
1.4 KiB
VHDL
52 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.test_package.all;
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use work.rtps_package.all;
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-- TODO: Remove alignment logic for RTPS Submessages, since all Submessages are 32-bit aligned
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-- Checksum has to be checked before
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entity test is
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port (
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clk : in std_logic; -- Input Clock
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reset : in std_logic; -- Synchronous Reset
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input : in std_logic_vector(31 downto 0);
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cnt : out natural range 0 to NUM_ENDPOINTS
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);
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end entity;
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architecture arch of test is
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signal test_var : natural := 0;
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-- Compares argument 'ref' with every element of 'ar', and returns the index of the last match.
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-- If no match is found, array length is returned.
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function match_id_endpoint (ref : std_logic_vector(ENTITYID_WIDTH-1 downto 0); ar : ENTITYID_TYPE) return natural is
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variable id : natural := 0;
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begin
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id := ar'length;
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for i in 0 to ar'length-1 loop
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if(ref = ar(i)) then
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id := i;
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end if;
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end loop;
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return id;
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end function;
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begin
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process(all)
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begin
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cnt <= 0;
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if (test_var < to_unsigned(input)) then
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cnt <= match_id_endpoint(input, ENTITYID);
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end if;
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end process;
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end architecture;
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