af1de8bab8
Templates with the pre-defined code hull for the reader_wrapper, writer_wrapper, and key_holder were created. A "cookbook" of how to expand this TEMPLATES to create type specific IDL conversions was also added. The "code generation" is kept general to allow a code generator to automatically produce this wrappers in the future.
69 lines
2.1 KiB
VHDL
69 lines
2.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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architecture arch of key_hash_generator is
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type STAGE_TYPE is (IDLE, GEN_CHECKSUM, FINALIZE);
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signal stage, stage_next : STAGE_TYPE := IDLE;
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signal checksum, checksum_next : std_logic_vector(127 downto 0) := (others => '0');
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signal done_sig, done_sig_next : std_logic := '0';
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begin
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done <= done_sig;
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key_hash <= checksum;
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checksum_prc : process(all)
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begin
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-- DEFAULT
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stage_next <= stage;
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checksum_next <= checksum;
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done_sig_next <= '0';
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ack <= '0';
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case (stage) is
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when IDLE =>
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if (start = '1') then
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ack <= '1';
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stage_next <= GEN_CHECKSUM;
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-- Reset
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checksum_next <= (others => '0');
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end if;
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when GEN_CHECKSUM =>
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ready_in <= '1';
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-- Input Guard
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if (valid_in = '1') then
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checksum_next <= std_logic_vector(unsigned(checksum) + resize(unsigned(data_in),checksum'length));
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-- Last Word
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if (last_word_in = '1') then
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stage_next <= FINALIZE;
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end if;
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end if;
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when FINALIZE =>
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checksum_next <= std_logic_vector(-signed(checksum)); -- Two's Complement
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done_sig_next <= '1';
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stage_next <= IDLE;
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when others =>
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null;
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end case;
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end process;
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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stage <= IDLE;
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done_sig <= '0';
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checksum <= (others => '0');
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else
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stage <= stage_next;
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done_sig <= done_sig_next;
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checksum <= checksum_next;
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end if;
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end if;
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end process;
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end architecture; |