b47d409f13
Remove non-Quartus-supported VHDL 2008 features. Remove inferred Latches. Add test Entities to see resulting hw synthesis of various code segments.
74 lines
1.8 KiB
VHDL
74 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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-- Test how FSM states guarded with a synthesis guard are handled.
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entity test3 is
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generic (
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BUILD : boolean := FALSE
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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input : in std_logic_vector(31 downto 0);
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output : out std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arch of test3 is
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type STAGE_TYPE is (IDLE, STATE1, STATE2);
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signal stage, stage_next : STAGE_TYPE := IDLE;
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begin
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process(all)
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begin
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stage_next <= stage;
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output <= (others => '0');
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case (stage) is
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when IDLE =>
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case (input) is
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when x"00000000" =>
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if (BUILD) then
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stage_next <= STATE1;
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else
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stage_next <= STATE2;
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end if;
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when x"00000001" =>
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stage_next <= STATE2;
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when others =>
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null;
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end case;
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when STATE1 =>
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if (BUILD) then
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stage_next <= IDLE;
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output <= x"DEADBEEF";
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end if;
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when STATE2 =>
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stage_next <= IDLE;
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output <= x"BEEFDEAD";
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when others =>
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null;
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end case;
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end process;
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sync : process(all)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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stage <= IDLE;
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else
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stage <= stage_next;
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end if;
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end if;
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end process;
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end architecture;
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