67 lines
2.1 KiB
VHDL
67 lines
2.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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Library xpm;
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use xpm.vcomponents.all;
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entity single_port_ram is
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generic (
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ADDR_WIDTH : integer := 8;
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DATA_WIDTH : integer := 12;
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MEMORY_SIZE : integer := DATA_WIDTH*(2**ADDR_WIDTH)
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);
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port (
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clk : in std_logic;
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addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
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wen : in std_logic;
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ren : in std_logic;
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wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
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rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of single_port_ram is
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begin
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xpm_memory_spram_inst : xpm_memory_spram
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generic map (
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ADDR_WIDTH_A => ADDR_WIDTH,
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AUTO_SLEEP_TIME => 0,
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BYTE_WRITE_WIDTH_A => DATA_WIDTH,
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ECC_MODE => "no_ecc",
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MEMORY_INIT_FILE => "none",
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MEMORY_INIT_PARAM => "0",
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MEMORY_OPTIMIZATION => "true",
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MEMORY_PRIMITIVE => "auto",
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MEMORY_SIZE => MEMORY_SIZE,
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MESSAGE_CONTROL => 0,
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READ_DATA_WIDTH_A => DATA_WIDTH,
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READ_LATENCY_A => 1,
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READ_RESET_VALUE_A => "0",
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RST_MODE_A => "SYNC",
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USE_MEM_INIT => 1,
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WAKEUP_TIME => "disable_sleep",
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WRITE_DATA_WIDTH_A => DATA_WIDTH,
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WRITE_MODE_A => "read_first"
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)
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port map (
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dbiterra => open,
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douta => rd_data,
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sbiterra => open,
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addra => addr,
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clka => clk,
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dina => wr_data,
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ena => (ren or wen),
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injectdbiterra => '0',
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injectsbiterra => '0',
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regcea => '1',
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rsta => '0',
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sleep => '0',
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wea => (others => wen) --1-bit Vector
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);
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end architecture;
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