55 lines
1.8 KiB
VHDL
55 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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entity single_port_ram is
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generic (
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ADDR_WIDTH : natural := 8;
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DATA_WIDTH : natural := 12;
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MEMORY_DEPTH : natural := 256
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);
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port (
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clk : in std_logic;
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addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
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wen : in std_logic;
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ren : in std_logic;
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wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
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rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of single_port_ram is
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begin
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altsyncram_component : altsyncram
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generic map (
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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intended_device_family => "Cyclone V",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => MEMORY_DEPTH,
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operation_mode => "SINGLE_PORT",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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power_up_uninitialized => "FALSE",
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read_during_write_mode_port_a => "DONT_CARE",
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widthad_a => ADDR_WIDTH,
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width_a => DATA_WIDTH,
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width_byteena_a => 1
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)
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port map (
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address_a => addr,
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clock0 => clk,
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data_a => wr_data,
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rden_a => ren,
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wren_a => wen,
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q_a => rd_data
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);
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end architecture;
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