46ca2228b6
Simple Dual Port (Read and Write Port), and True Dual Port RAM implementations, together with their respective Altera implementations were added. The 'arch' Architectures should have the same behaviour as the Altera Implementations (single_port_ram was modified to achieve that)
4 lines
96 B
VHDL
4 lines
96 B
VHDL
configuration dual_port_ram_cfg of dual_port_ram is
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for arch
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end for;
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end configuration; |