52 lines
1.7 KiB
VHDL
52 lines
1.7 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mult is
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generic (
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PIPELINE_STAGES : natural := 1;
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DATAA_WIDTH : natural;
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DATAB_WIDTH : natural;
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DATAB_CONST : boolean := FALSE
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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dataa : in std_logic_vector(DATAA_WIDTH-1 downto 0);
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datab : in std_logic_vector(DATAB_WIDTH-1 downto 0);
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result : out std_logic_vector(DATAA_WIDTH+DATAB_WIDTH-1 downto 0)
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);
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end entity;
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architecture arch of mult is
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type PIPELINE_STAGE_ARRAY is array (0 to PIPELINE_STAGES-1) of std_logic_vector(DATAA_WIDTH+DATAB_WIDTH-1 downto 0);
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signal pipeline : PIPELINE_STAGE_ARRAY := (others => (others => '0'));
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begin
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assert (PIPELINE_STAGES >= 1) report "MULT has to have at least 1 pipeline stage" severity FAILURE;
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result <= pipeline(PIPELINE_STAGES-1);
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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pipeline <= (others => (others => '0'));
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else
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pipeline(0) <= std_logic_vector(unsigned(dataa) * unsigned(datab));
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if (PIPELINE_STAGES > 1) then
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for i in 1 to PIPELINE_STAGES-1 loop
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pipeline(i) <= pipeline(i-1);
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end loop;
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end if;
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end if;
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end if;
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end process;
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end architecture; |