Greek64
5d9acb6f41
QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
42 lines
1.4 KiB
VHDL
42 lines
1.4 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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architecture altera of single_port_ram is
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begin
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altsyncram_component : altsyncram
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generic map (
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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intended_device_family => "Cyclone V",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => MEMORY_DEPTH,
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operation_mode => "SINGLE_PORT",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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power_up_uninitialized => "FALSE",
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read_during_write_mode_port_a => "DONT_CARE",
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widthad_a => ADDR_WIDTH,
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width_a => DATA_WIDTH,
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width_byteena_a => 1
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)
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port map (
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address_a => addr,
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clock0 => clk,
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data_a => wr_data,
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rden_a => ren,
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wren_a => wen,
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q_a => rd_data
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);
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end architecture;
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