10cda546bf
- IPv4 RFC - FPGA Network Stack Master Thesis * Updated .gitignore * Added Single Port RAM - Xillinx Specific * Added IPv4 Parser - Dynamic Re-assembly Buffer selection - Main entity documentation missing - Synthesized, but not tested or simulated * Added Vivado (Zedboard) project for synthesis testing
6 lines
274 B
Tcl
6 lines
274 B
Tcl
#100 Mhz
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create_clock -period 10.000 -name sys_clk -waveform {0.000 5.000} [get_ports clk]
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# 166 Mhz
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#create_clock -period 6.000 -name sys_clk -waveform {0.000 3.000} [get_ports clk]
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# 200 Mhz
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#create_clock -period 5.000 -name sys_clk -waveform {0.000 2.500} [get_ports clk] |