46ca2228b6
Simple Dual Port (Read and Write Port), and True Dual Port RAM implementations, together with their respective Altera implementations were added. The 'arch' Architectures should have the same behaviour as the Altera Implementations (single_port_ram was modified to achieve that)
59 lines
2.4 KiB
VHDL
59 lines
2.4 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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architecture altera of true_dual_port_ram is
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begin
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altsyncram_component : altsyncram
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generic map (
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address_reg_b => "CLOCK0",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_b => "BYPASS",
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clock_enable_output_a => "BYPASS",
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clock_enable_output_b => "BYPASS",
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indata_reg_b => "CLOCK0",
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intended_device_family => "Cyclone V",
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lpm_type => "altsyncram",
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numwords_a => MEMORY_DEPTH,
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numwords_b => MEMORY_DEPTH,
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operation_mode => "BIDIR_DUAL_PORT",
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outdata_aclr_a => "NONE",
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outdata_aclr_b => "NONE",
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_b => "UNREGISTERED",
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power_up_uninitialized => "FALSE",
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read_during_write_mode_mixed_ports => "DONT_CARE",
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read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
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read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
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widthad_a => ADDR_WIDTH,
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widthad_b => ADDR_WIDTH,
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width_a => DATA_WIDTH,
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width_b => DATA_WIDTH,
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width_byteena_a => 1,
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width_byteena_b => 1,
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wrcontrol_wraddress_reg_b => "CLOCK0"
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)
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port map (
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address_a => addr_a,
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address_b => addr_b,
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clock0 => clk,
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data_a => wr_data_a,
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data_b => wr_data_b,
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rden_a => ren_a,
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rden_b => ren_b,
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wren_a => wen_a,
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wren_b => wen_b,
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q_a => rd_data_a,
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q_b => rd_data_b
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);
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end architecture;
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