84 lines
2.5 KiB
VHDL
84 lines
2.5 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rtps_package.all;
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use work.rtps_config_package.all;
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architecture arch of key_hash_generator is
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constant MAX_CNT_BOUND : natural := (KEY_HASH_WIDTH/data_in'length);
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type STAGE_TYPE is (IDLE, GEN_KEY_HASH, FINALIZE);
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signal stage, stage_next : STAGE_TYPE;
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signal cnt, cnt_next : natural range 0 to MAX_CNT_BOUND-1;
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signal kh, kh_next : std_logic_vector(KEY_HASH_WIDTH-1 downto 0);
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begin
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key_hash <= kh;
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kh_prc : process(all)
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begin
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-- DEFAULT
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stage_next <= stage;
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kh_next <= kh;
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cnt_next <= cnt;
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-- DEFAULT Unregistered
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ack <= '0';
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ready_in <= '0';
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done <= '0';
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case (stage) is
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when IDLE =>
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if (start = '1') then
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ack <= '1';
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stage_next <= GEN_KEY_HASH;
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-- Reset
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kh_next <= (others => '0');
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cnt_next <= 0;
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end if;
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when GEN_KEY_HASH =>
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ready_in <= '1';
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-- Input Guard
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if (valid_in = '1') then
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kh_next <= write_sub_vector(kh, data_in, cnt, TRUE);
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-- Last Word
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if (last_word_in = '1') then
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stage_next <= FINALIZE;
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elsif (cnt = MAX_CNT_BOUND-1) then
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-- Reset (Prevent overflow)
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cnt_next <= 0;
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else
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cnt_next <= cnt + 1;
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end if;
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end if;
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when FINALIZE =>
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done <= '1';
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stage_next <= IDLE;
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when others =>
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null;
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end case;
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end process;
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sync_prc : process(clk)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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stage <= IDLE;
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cnt <= 0;
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kh <= (others => '0');
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else
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stage <= stage_next;
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cnt <= cnt_next;
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kh <= kh_next;
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end if;
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end if;
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end process;
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end architecture;
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