rtps-fpga/sim/L0_rtps_writer_test1.do
Greek64 f6fec48a0e Convert rtps_writer to Vector Endpoint
rtps_writer now can be configured to simulate multiple endpoints. All
Testbenched were modified to reflect and test this change.
Packages were extended with array definitions.
2022-04-05 17:18:07 +02:00

72 lines
4.2 KiB
Plaintext

onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider SYSTEM
add wave -noupdate /l0_rtps_writer_test1/uut/clk
add wave -noupdate /l0_rtps_writer_test1/uut/reset
add wave -noupdate -divider INPUT
add wave -noupdate /l0_rtps_writer_test1/uut/empty_meta
add wave -noupdate /l0_rtps_writer_test1/uut/rd_meta
add wave -noupdate /l0_rtps_writer_test1/uut/last_word_in_meta
add wave -noupdate -radix hexadecimal /l0_rtps_writer_test1/uut/data_in_meta
add wave -noupdate -divider OUTPUT
add wave -noupdate /l0_rtps_writer_test1/uut/start_hc
add wave -noupdate /l0_rtps_writer_test1/uut/opcode_hc
add wave -noupdate /l0_rtps_writer_test1/uut/ack_hc
add wave -noupdate /l0_rtps_writer_test1/uut/done_hc
add wave -noupdate -divider {MAIN FSM}
add wave -noupdate /l0_rtps_writer_test1/uut/stage
add wave -noupdate /l0_rtps_writer_test1/uut/cnt
add wave -noupdate -radix unsigned /l0_rtps_writer_test1/uut/ind
add wave -noupdate /l0_rtps_writer_test1/uut/w_map
add wave -noupdate -divider {MEMORY FSM}
add wave -noupdate /l0_rtps_writer_test1/uut/mem_op_done
add wave -noupdate /l0_rtps_writer_test1/uut/mem_op_start
add wave -noupdate /l0_rtps_writer_test1/uut/mem_opcode
add wave -noupdate /l0_rtps_writer_test1/uut/mem_stage
add wave -noupdate /l0_rtps_writer_test1/uut/mem_cnt
add wave -noupdate -radix unsigned /l0_rtps_writer_test1/uut/mem_occupied_head
add wave -noupdate -radix unsigned /l0_rtps_writer_test1/uut/mem_empty_head
add wave -noupdate -radix unsigned /l0_rtps_writer_test1/uut/mem_addr_base
add wave -noupdate -expand -group MEM0 -radix unsigned /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/addr
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/read
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/ready_in
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/valid_in
add wave -noupdate -expand -group MEM0 -radix hexadecimal /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/data_in
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/ready_out
add wave -noupdate -expand -group MEM0 /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/valid_out
add wave -noupdate -expand -group MEM0 -radix hexadecimal /l0_rtps_writer_test1/uut/mem_ctrl_gen(0)/mem_ctrl_inst/data_out
add wave -noupdate -group MEM1 -radix unsigned /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/addr
add wave -noupdate -group MEM1 /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/read
add wave -noupdate -group MEM1 /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/ready_in
add wave -noupdate -group MEM1 /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/valid_in
add wave -noupdate -group MEM1 -radix hexadecimal /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/data_in
add wave -noupdate -group MEM1 /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/ready_out
add wave -noupdate -group MEM1 /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/valid_out
add wave -noupdate -group MEM1 -radix hexadecimal /l0_rtps_writer_test1/uut/mem_ctrl_gen(1)/mem_ctrl_inst/data_out
add wave -noupdate -divider TESTBENCH
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1/start
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1/cnt_stim
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1/packet_sent
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1/mem_check_done
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1/stim_done
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1/test_done
add wave -noupdate -group TESTBENCH /l0_rtps_writer_test1/uut/idle_sig
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {Begin {8325000 ps} 1} {Error {9725000 ps} 1} {Cursor {393312 ps} 0}
quietly wave cursor active 3
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {1024 ns}