John Daktylidis
a1e0297fcb
The Golden Hardware Reference Design (GHRD) is used to implement designs with PS support. The UDP/IP stack of the Linux running on the PS is used to move UDP packets to/from the PL.
265 lines
15 KiB
Verilog
265 lines
15 KiB
Verilog
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//=======================================================
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// This code is generated by Terasic System Builder
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//=======================================================
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module DE10_NANO_SoC_GHRD(
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//////////// CLOCK //////////
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input FPGA_CLK1_50,
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input FPGA_CLK2_50,
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input FPGA_CLK3_50,
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//////////// HDMI //////////
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inout HDMI_I2C_SCL,
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inout HDMI_I2C_SDA,
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inout HDMI_I2S,
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inout HDMI_LRCLK,
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inout HDMI_MCLK,
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inout HDMI_SCLK,
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output HDMI_TX_CLK,
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output [23: 0] HDMI_TX_D,
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output HDMI_TX_DE,
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output HDMI_TX_HS,
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input HDMI_TX_INT,
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output HDMI_TX_VS,
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//////////// HPS //////////
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inout HPS_CONV_USB_N,
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output [14: 0] HPS_DDR3_ADDR,
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output [ 2: 0] HPS_DDR3_BA,
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output HPS_DDR3_CAS_N,
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output HPS_DDR3_CK_N,
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output HPS_DDR3_CK_P,
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output HPS_DDR3_CKE,
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output HPS_DDR3_CS_N,
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output [ 3: 0] HPS_DDR3_DM,
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inout [31: 0] HPS_DDR3_DQ,
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inout [ 3: 0] HPS_DDR3_DQS_N,
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inout [ 3: 0] HPS_DDR3_DQS_P,
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output HPS_DDR3_ODT,
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output HPS_DDR3_RAS_N,
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output HPS_DDR3_RESET_N,
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input HPS_DDR3_RZQ,
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output HPS_DDR3_WE_N,
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output HPS_ENET_GTX_CLK,
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inout HPS_ENET_INT_N,
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output HPS_ENET_MDC,
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inout HPS_ENET_MDIO,
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input HPS_ENET_RX_CLK,
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input [ 3: 0] HPS_ENET_RX_DATA,
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input HPS_ENET_RX_DV,
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output [ 3: 0] HPS_ENET_TX_DATA,
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output HPS_ENET_TX_EN,
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inout HPS_GSENSOR_INT,
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inout HPS_I2C0_SCLK,
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inout HPS_I2C0_SDAT,
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inout HPS_I2C1_SCLK,
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inout HPS_I2C1_SDAT,
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inout HPS_KEY,
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inout HPS_LED,
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inout HPS_LTC_GPIO,
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output HPS_SD_CLK,
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inout HPS_SD_CMD,
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inout [ 3: 0] HPS_SD_DATA,
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output HPS_SPIM_CLK,
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input HPS_SPIM_MISO,
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output HPS_SPIM_MOSI,
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inout HPS_SPIM_SS,
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input HPS_UART_RX,
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output HPS_UART_TX,
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input HPS_USB_CLKOUT,
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inout [ 7: 0] HPS_USB_DATA,
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input HPS_USB_DIR,
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input HPS_USB_NXT,
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output HPS_USB_STP,
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//////////// KEY //////////
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input [ 1: 0] KEY,
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//////////// LED //////////
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output [ 7: 0] LED,
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//////////// SW //////////
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input [ 3: 0] SW
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);
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//=======================================================
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// REG/WIRE declarations
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//=======================================================
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wire hps_fpga_reset_n;
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wire [1: 0] fpga_debounced_buttons;
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wire [6: 0] fpga_led_internal;
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wire [2: 0] hps_reset_req;
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wire hps_cold_reset;
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wire hps_warm_reset;
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wire hps_debug_reset;
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wire [27: 0] stm_hw_events;
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wire fpga_clk_50;
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// connection of internal logics
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assign LED[7: 1] = fpga_led_internal;
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assign fpga_clk_50 = FPGA_CLK1_50;
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assign stm_hw_events = {{15{1'b0}}, SW, fpga_led_internal, fpga_debounced_buttons};
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//=======================================================
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// Structural coding
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//=======================================================
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soc_system u0(
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//Clock&Reset
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.clk_clk(FPGA_CLK1_50), // clk.clk
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.reset_reset_n(hps_fpga_reset_n), // reset.reset_n
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//HPS ddr3
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.memory_mem_a(HPS_DDR3_ADDR), // memory.mem_a
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.memory_mem_ba(HPS_DDR3_BA), // .mem_ba
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.memory_mem_ck(HPS_DDR3_CK_P), // .mem_ck
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.memory_mem_ck_n(HPS_DDR3_CK_N), // .mem_ck_n
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.memory_mem_cke(HPS_DDR3_CKE), // .mem_cke
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.memory_mem_cs_n(HPS_DDR3_CS_N), // .mem_cs_n
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.memory_mem_ras_n(HPS_DDR3_RAS_N), // .mem_ras_n
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.memory_mem_cas_n(HPS_DDR3_CAS_N), // .mem_cas_n
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.memory_mem_we_n(HPS_DDR3_WE_N), // .mem_we_n
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.memory_mem_reset_n(HPS_DDR3_RESET_N), // .mem_reset_n
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.memory_mem_dq(HPS_DDR3_DQ), // .mem_dq
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.memory_mem_dqs(HPS_DDR3_DQS_P), // .mem_dqs
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.memory_mem_dqs_n(HPS_DDR3_DQS_N), // .mem_dqs_n
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.memory_mem_odt(HPS_DDR3_ODT), // .mem_odt
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.memory_mem_dm(HPS_DDR3_DM), // .mem_dm
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.memory_oct_rzqin(HPS_DDR3_RZQ), // .oct_rzqin
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//HPS ethernet
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.hps_0_hps_io_hps_io_emac1_inst_TX_CLK(HPS_ENET_GTX_CLK), // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
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.hps_0_hps_io_hps_io_emac1_inst_TXD0(HPS_ENET_TX_DATA[0]), // .hps_io_emac1_inst_TXD0
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.hps_0_hps_io_hps_io_emac1_inst_TXD1(HPS_ENET_TX_DATA[1]), // .hps_io_emac1_inst_TXD1
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.hps_0_hps_io_hps_io_emac1_inst_TXD2(HPS_ENET_TX_DATA[2]), // .hps_io_emac1_inst_TXD2
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.hps_0_hps_io_hps_io_emac1_inst_TXD3(HPS_ENET_TX_DATA[3]), // .hps_io_emac1_inst_TXD3
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.hps_0_hps_io_hps_io_emac1_inst_RXD0(HPS_ENET_RX_DATA[0]), // .hps_io_emac1_inst_RXD0
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.hps_0_hps_io_hps_io_emac1_inst_MDIO(HPS_ENET_MDIO), // .hps_io_emac1_inst_MDIO
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.hps_0_hps_io_hps_io_emac1_inst_MDC(HPS_ENET_MDC), // .hps_io_emac1_inst_MDC
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.hps_0_hps_io_hps_io_emac1_inst_RX_CTL(HPS_ENET_RX_DV), // .hps_io_emac1_inst_RX_CTL
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.hps_0_hps_io_hps_io_emac1_inst_TX_CTL(HPS_ENET_TX_EN), // .hps_io_emac1_inst_TX_CTL
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.hps_0_hps_io_hps_io_emac1_inst_RX_CLK(HPS_ENET_RX_CLK), // .hps_io_emac1_inst_RX_CLK
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.hps_0_hps_io_hps_io_emac1_inst_RXD1(HPS_ENET_RX_DATA[1]), // .hps_io_emac1_inst_RXD1
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.hps_0_hps_io_hps_io_emac1_inst_RXD2(HPS_ENET_RX_DATA[2]), // .hps_io_emac1_inst_RXD2
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.hps_0_hps_io_hps_io_emac1_inst_RXD3(HPS_ENET_RX_DATA[3]), // .hps_io_emac1_inst_RXD3
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//HPS SD card
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.hps_0_hps_io_hps_io_sdio_inst_CMD(HPS_SD_CMD), // .hps_io_sdio_inst_CMD
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.hps_0_hps_io_hps_io_sdio_inst_D0(HPS_SD_DATA[0]), // .hps_io_sdio_inst_D0
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.hps_0_hps_io_hps_io_sdio_inst_D1(HPS_SD_DATA[1]), // .hps_io_sdio_inst_D1
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.hps_0_hps_io_hps_io_sdio_inst_CLK(HPS_SD_CLK), // .hps_io_sdio_inst_CLK
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.hps_0_hps_io_hps_io_sdio_inst_D2(HPS_SD_DATA[2]), // .hps_io_sdio_inst_D2
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.hps_0_hps_io_hps_io_sdio_inst_D3(HPS_SD_DATA[3]), // .hps_io_sdio_inst_D3
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//HPS USB
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.hps_0_hps_io_hps_io_usb1_inst_D0(HPS_USB_DATA[0]), // .hps_io_usb1_inst_D0
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.hps_0_hps_io_hps_io_usb1_inst_D1(HPS_USB_DATA[1]), // .hps_io_usb1_inst_D1
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.hps_0_hps_io_hps_io_usb1_inst_D2(HPS_USB_DATA[2]), // .hps_io_usb1_inst_D2
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.hps_0_hps_io_hps_io_usb1_inst_D3(HPS_USB_DATA[3]), // .hps_io_usb1_inst_D3
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.hps_0_hps_io_hps_io_usb1_inst_D4(HPS_USB_DATA[4]), // .hps_io_usb1_inst_D4
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.hps_0_hps_io_hps_io_usb1_inst_D5(HPS_USB_DATA[5]), // .hps_io_usb1_inst_D5
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.hps_0_hps_io_hps_io_usb1_inst_D6(HPS_USB_DATA[6]), // .hps_io_usb1_inst_D6
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.hps_0_hps_io_hps_io_usb1_inst_D7(HPS_USB_DATA[7]), // .hps_io_usb1_inst_D7
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.hps_0_hps_io_hps_io_usb1_inst_CLK(HPS_USB_CLKOUT), // .hps_io_usb1_inst_CLK
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.hps_0_hps_io_hps_io_usb1_inst_STP(HPS_USB_STP), // .hps_io_usb1_inst_STP
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.hps_0_hps_io_hps_io_usb1_inst_DIR(HPS_USB_DIR), // .hps_io_usb1_inst_DIR
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.hps_0_hps_io_hps_io_usb1_inst_NXT(HPS_USB_NXT), // .hps_io_usb1_inst_NXT
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//HPS SPI
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.hps_0_hps_io_hps_io_spim1_inst_CLK(HPS_SPIM_CLK), // .hps_io_spim1_inst_CLK
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.hps_0_hps_io_hps_io_spim1_inst_MOSI(HPS_SPIM_MOSI), // .hps_io_spim1_inst_MOSI
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.hps_0_hps_io_hps_io_spim1_inst_MISO(HPS_SPIM_MISO), // .hps_io_spim1_inst_MISO
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.hps_0_hps_io_hps_io_spim1_inst_SS0(HPS_SPIM_SS), // .hps_io_spim1_inst_SS0
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//HPS UART
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.hps_0_hps_io_hps_io_uart0_inst_RX(HPS_UART_RX), // .hps_io_uart0_inst_RX
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.hps_0_hps_io_hps_io_uart0_inst_TX(HPS_UART_TX), // .hps_io_uart0_inst_TX
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//HPS I2C1
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.hps_0_hps_io_hps_io_i2c0_inst_SDA(HPS_I2C0_SDAT), // .hps_io_i2c0_inst_SDA
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.hps_0_hps_io_hps_io_i2c0_inst_SCL(HPS_I2C0_SCLK), // .hps_io_i2c0_inst_SCL
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//HPS I2C2
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.hps_0_hps_io_hps_io_i2c1_inst_SDA(HPS_I2C1_SDAT), // .hps_io_i2c1_inst_SDA
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.hps_0_hps_io_hps_io_i2c1_inst_SCL(HPS_I2C1_SCLK), // .hps_io_i2c1_inst_SCL
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//GPIO
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.hps_0_hps_io_hps_io_gpio_inst_GPIO09(HPS_CONV_USB_N), // .hps_io_gpio_inst_GPIO09
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.hps_0_hps_io_hps_io_gpio_inst_GPIO35(HPS_ENET_INT_N), // .hps_io_gpio_inst_GPIO35
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.hps_0_hps_io_hps_io_gpio_inst_GPIO40(HPS_LTC_GPIO), // .hps_io_gpio_inst_GPIO40
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.hps_0_hps_io_hps_io_gpio_inst_GPIO53(HPS_LED), // .hps_io_gpio_inst_GPIO53
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.hps_0_hps_io_hps_io_gpio_inst_GPIO54(HPS_KEY), // .hps_io_gpio_inst_GPIO54
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.hps_0_hps_io_hps_io_gpio_inst_GPIO61(HPS_GSENSOR_INT), // .hps_io_gpio_inst_GPIO61
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//FPGA Partion
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.hps_0_h2f_reset_reset_n(hps_fpga_reset_n), // hps_0_h2f_reset.reset_n
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.hps_0_f2h_cold_reset_req_reset_n(~hps_cold_reset), // hps_0_f2h_cold_reset_req.reset_n
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.hps_0_f2h_debug_reset_req_reset_n(~hps_debug_reset), // hps_0_f2h_debug_reset_req.reset_n
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.hps_0_f2h_stm_hw_events_stm_hwevents(stm_hw_events), // hps_0_f2h_stm_hw_events.stm_hwevents
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.hps_0_f2h_warm_reset_req_reset_n(~hps_warm_reset), // hps_0_f2h_warm_reset_req.reset_n
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);
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// Debounce logic to clean out glitches within 1ms
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debounce debounce_inst(
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.clk(fpga_clk_50),
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.reset_n(hps_fpga_reset_n),
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.data_in(KEY),
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.data_out(fpga_debounced_buttons)
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);
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defparam debounce_inst.WIDTH = 2;
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defparam debounce_inst.POLARITY = "LOW";
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defparam debounce_inst.TIMEOUT = 50000; // at 50Mhz this is a debounce time of 1ms
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defparam debounce_inst.TIMEOUT_WIDTH = 16; // ceil(log2(TIMEOUT))
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// Source/Probe megawizard instance
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hps_reset hps_reset_inst(
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.source_clk(fpga_clk_50),
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.source(hps_reset_req)
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);
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altera_edge_detector pulse_cold_reset(
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.clk(fpga_clk_50),
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.rst_n(hps_fpga_reset_n),
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.signal_in(hps_reset_req[0]),
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.pulse_out(hps_cold_reset)
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);
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defparam pulse_cold_reset.PULSE_EXT = 6;
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defparam pulse_cold_reset.EDGE_TYPE = 1;
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defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
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altera_edge_detector pulse_warm_reset(
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.clk(fpga_clk_50),
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.rst_n(hps_fpga_reset_n),
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.signal_in(hps_reset_req[1]),
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.pulse_out(hps_warm_reset)
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);
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defparam pulse_warm_reset.PULSE_EXT = 2;
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defparam pulse_warm_reset.EDGE_TYPE = 1;
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defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
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altera_edge_detector pulse_debug_reset(
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.clk(fpga_clk_50),
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.rst_n(hps_fpga_reset_n),
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.signal_in(hps_reset_req[2]),
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.pulse_out(hps_debug_reset)
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);
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defparam pulse_debug_reset.PULSE_EXT = 32;
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defparam pulse_debug_reset.EDGE_TYPE = 1;
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defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
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reg [25: 0] counter;
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reg led_level;
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always @(posedge fpga_clk_50 or negedge hps_fpga_reset_n) begin
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if (~hps_fpga_reset_n) begin
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counter <= 0;
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led_level <= 0;
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end
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else if (counter == 24999999) begin
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counter <= 0;
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led_level <= ~led_level;
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end
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else
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counter <= counter + 1'b1;
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end
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assign LED[0] = led_level;
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endmodule
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