Greek64
5d9acb6f41
QSYS does not allow to change the VHDL version of processed files. All respective files have to have a comment directive forcing the VHDL version.
71 lines
2.1 KiB
VHDL
71 lines
2.1 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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-- Test synthesis of array indexing
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entity test4 is
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port (
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clk : in std_logic;
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reset : in std_logic;
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input : in std_logic_vector(31 downto 0);
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input2 : in std_logic_vector(31 downto 0);
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output : out std_logic_vector(31 downto 0)
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);
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end entity;
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architecture arch of test4 is
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type TEST_ARRAY_TYPE is array (0 to 3) of std_logic_vector(31 downto 0);
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signal test_array : TEST_ARRAY_TYPE;
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begin
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process (all)
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begin
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if rising_edge(clk) then
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if (reset = '1') then
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output <= (others => '0');
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test_array <= (others => (others => '0'));
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else
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case (to_integer(unsigned(input))) is
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when 0 =>
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output <= test_array(0);
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test_array(0) <= input2;
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when 1 =>
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output <= test_array(1);
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test_array(1) <= input2;
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when 2 =>
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output <= test_array(2);
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test_array(2) <= input2;
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when 3 =>
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output <= test_array(3);
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test_array(3) <= input2;
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when others =>
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end case;
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end if;
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end if;
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end process;
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-- process (all)
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-- begin
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-- if rising_edge(clk) then
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-- if (reset = '1') then
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-- output <= (others => '0');
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-- test_array <= (others => (others => '0'));
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-- else
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-- test_array(to_integer(unsigned(input))) <= input2;
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-- output <= test_array(to_integer(unsigned(input)));
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-- end if;
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-- end if;
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-- end process;
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end architecture;
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