86 lines
3.5 KiB
VHDL
86 lines
3.5 KiB
VHDL
-- altera vhdl_input_version vhdl_2008
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-- XXX: QSYS Fix (https://www.intel.com/content/www/us/en/support/programmable/articles/000079458.html)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.math_pkg.all;
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use work.rtps_package.all;
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use work.user_config.all;
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use work.rtps_config_package.all;
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entity rtps_reader_syn is
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port (
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-- SYSTEM
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clk : in std_logic;
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reset : in std_logic;
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time : in TIME_TYPE;
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-- FROM RTPS HANDLER (USER TRAFFIC)
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empty_user : in std_logic_vector(0 to 0);
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rd_user : out std_logic;
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data_in_user : in std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_in_user : in std_logic;
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-- FROM RTPS BUILTIN ENDPOINT (META TRAFFIC)
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empty_meta : in std_logic_vector(0 to 0);
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rd_meta : out std_logic;
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data_in_meta : in std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_in_meta : in std_logic;
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-- RTPS OUTPUT
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full_ro : in std_logic;
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wr_ro : out std_logic;
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data_out_ro : out std_logic_vector(WORD_WIDTH-1 downto 0);
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last_word_out_ro : out std_logic;
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-- TO HISTORY CACHE
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start_hc : out std_logic_vector(0 to 0);
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opcode_hc : out HISTORY_CACHE_OPCODE_ARRAY_TYPE(0 to 0);
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ack_hc : in std_logic_vector(0 to 0);
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done_hc : in std_logic_vector(0 to 0);
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ret_hc : in HISTORY_CACHE_RESPONSE_ARRAY_TYPE(0 to 0);
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valid_out_hc : out std_logic_vector(0 to 0);
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ready_out_hc : in std_logic_vector(0 to 0);
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data_out_hc : out WORD_ARRAY_TYPE(0 to 0);
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last_word_out_hc : out std_logic_vector(0 to 0)
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);
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end entity;
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architecture arch of rtps_reader_syn is
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begin
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if_gen : if (NUM_READERS > 0) generate
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syn_inst : entity work.rtps_reader(arch)
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generic map (
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NUM_READERS => 1,
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CONFIG_ARRAY => to_QUARTUS_CONFIG_ARRAY_TYPE(ENDPOINT_CONFIG(0 to 0)),
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ENTITYID => ENTITYID(0 to 0)
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)
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port map (
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clk => clk,
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reset => reset,
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time => time,
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empty_user => empty_user,
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rd_user => rd_user,
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data_in_user => data_in_user,
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last_word_in_user => last_word_in_user,
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empty_meta => empty_meta,
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rd_meta => rd_meta,
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data_in_meta => data_in_meta,
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last_word_in_meta => last_word_in_meta,
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full_ro => full_ro,
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wr_ro => wr_ro,
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data_out_ro => data_out_ro,
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last_word_out_ro => last_word_out_ro,
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start_hc => start_hc,
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opcode_hc => opcode_hc,
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ack_hc => ack_hc,
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done_hc => done_hc,
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ret_hc => ret_hc,
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data_out_hc => data_out_hc,
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valid_out_hc => valid_out_hc,
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ready_out_hc => ready_out_hc,
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last_word_out_hc => last_word_out_hc
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);
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end generate;
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end architecture;
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