rtps-fpga/src/Tests
Greek e33d982182 Add 'si_ack' to DDS Reader
Previously the simaple info data was valid for exectly 1 clock cycle,
in which the user had to pull the 'get_data' signal if he wanted the
associated payload.
This change allows the user to control how long the sample info data is
shown.
2021-11-03 18:33:35 +01:00
..
Level_0 Add 'si_ack' to DDS Reader 2021-11-03 18:33:35 +01:00
Level_1 Code Refactor 2021-05-15 20:39:56 +02:00
ScoreBoard_builtin_endpoint.vhd * Add modelsim.ini File in gitignore 2020-11-26 18:04:59 +01:00
ScoreBoard_test_memory.vhd * Add new DEFAULT values in packages 2020-11-23 12:20:05 +01:00
test_config.vhd Code Refactor 2021-05-15 20:39:56 +02:00
test_ram.vhd Memory Size of rtps_builtin_endpoint made Generic 2021-02-17 10:51:57 +01:00
testbench.pro Code Refactor 2021-05-15 20:39:56 +02:00