10cda546bf
- IPv4 RFC - FPGA Network Stack Master Thesis * Updated .gitignore * Added Single Port RAM - Xillinx Specific * Added IPv4 Parser - Dynamic Re-assembly Buffer selection - Main entity documentation missing - Synthesized, but not tested or simulated * Added Vivado (Zedboard) project for synthesis testing
18 lines
545 B
VHDL
18 lines
545 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package ip_package is
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-- TODO : Fix assignemnt of 1 wide array
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constant LAYER3_PROTOCOL_NUM : integer := 1;
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type LAYER3_PROTOCOL_TYPE is array (LAYER3_PROTOCOL_NUM-1 downto 0) of std_logic_vector(7 downto 0);
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constant LAYER3_PROTOCOLS : LAYER3_PROTOCOL_TYPE := (0 => x"11");
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--OUTPUT TYPES
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type IP_OUTPUT_TYPE is array (LAYER3_PROTOCOL_NUM-1 downto 0) of std_logic_vector(31 downto 0);
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end package;
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package body ip_package is
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end package body; |